The Gauss-Seidel method is effective to solve the traditional sparse linear system. In the paper, we define a class of sparse linear systems in iterative algorithm. The iterative method for linear system can be extend...The Gauss-Seidel method is effective to solve the traditional sparse linear system. In the paper, we define a class of sparse linear systems in iterative algorithm. The iterative method for linear system can be extended to the dummy sparse linear system. We apply the Gauss-Seidel method, which is one of the iterative methods for linear system, to the thermal model of floorplan of VLSI physical design. The experimental results of dummy sparse linear system are computed by using Gauss-Seidel method that have shown our theory analysis and extendibility. The iterative time of our incremental thermal model is 5 times faster than that of the inverting matrix method.展开更多
Floorplanning is a prominent area in the Very Large-Scale Integrated (VLSI) circuit design automation, because it influences the performance, size, yield and reliability of the VLSI chips. It is the process of estimat...Floorplanning is a prominent area in the Very Large-Scale Integrated (VLSI) circuit design automation, because it influences the performance, size, yield and reliability of the VLSI chips. It is the process of estimating the positions and shapes of the modules. A high packing density, small feature size and high clock frequency make the Integrated Circuit (IC) to dissipate large amount of heat. So, in this paper, a methodology is presented to distribute the temperature of the module on the layout while simultaneously optimizing the total area and wirelength by using a hybrid Particle Swarm Optimization-Harmony Search (HPSOHS) algorithm. This hybrid algorithm employs diversification technique (PSO) to obtain global optima and intensification strategy (HS) to achieve the best solution at the local level and Modified Corner List algorithm (MCL) for floorplan representation. A thermal modelling tool called hotspot tool is integrated with the proposed algorithm to obtain the temperature at the block level. The proposed algorithm is illustrated using Microelectronics Centre of North Carolina (MCNC) benchmark circuits. The results obtained are compared with the solutions derived from other stochastic algorithms and the proposed algorithm provides better solution.展开更多
We present a novel incremental algorithm for non-slicing floorplans based on the corner block list representation. The horizontal and vertical adjacency graphs are derived from the packing of the initial floorplanning...We present a novel incremental algorithm for non-slicing floorplans based on the corner block list representation. The horizontal and vertical adjacency graphs are derived from the packing of the initial floorplanning results. Based on the critical path and the accumulated slack distances we define,we choose the best position for insertion and do a series of operations incrementally, such as deleting modules, adding modules, and resizing modules quickly. This incremental floorplanning algorithm has a very high speed less than 1μm,which is one of the most important measures in this research. The algorithm preserves the original good performances on area and wire length. It can also supply other tools with good physical estimates for area, wire length, and other performance guidelines.展开更多
针对只有硬模块的布图规划问题,通常将其构建成组合优化模型,但求解过程时间成本高。为提高求解效率,提出了一种基于非光滑解析数学规划的布图规划算法。基于布图中器件的坐标表示,构建了一个泛化的非光滑解析数学规划模型,将不同场景...针对只有硬模块的布图规划问题,通常将其构建成组合优化模型,但求解过程时间成本高。为提高求解效率,提出了一种基于非光滑解析数学规划的布图规划算法。基于布图中器件的坐标表示,构建了一个泛化的非光滑解析数学规划模型,将不同场景下的布图规划问题的不同优化阶段处理为该泛化模型的特例,并利用共轭次梯度算法(conjugate sub-gradient algorithm,CSA)对其进行求解。针对固定轮廓布图规划问题,通过统一框架下的全局布图规划、合法化、局部优化三个阶段,实现了在固定轮廓约束下的线长优化。针对无固定轮廓约束问题,提出了带黄金分割策略的共轭次梯度算法(conjugate sub-gradient algorithm with golden section strategy,CSA_GSS),利用黄金分割策略缩小固定轮廓的面积,达到面积和线长双优化的效果。实验在GSRC测试电路上与基于B*-树表示的布图规划算法进行比较,该算法对于大规模电路在线长和时间方面均占据优势。实验结果表明,该算法能以更低的时间复杂度获得更优的线长。展开更多
文摘The Gauss-Seidel method is effective to solve the traditional sparse linear system. In the paper, we define a class of sparse linear systems in iterative algorithm. The iterative method for linear system can be extended to the dummy sparse linear system. We apply the Gauss-Seidel method, which is one of the iterative methods for linear system, to the thermal model of floorplan of VLSI physical design. The experimental results of dummy sparse linear system are computed by using Gauss-Seidel method that have shown our theory analysis and extendibility. The iterative time of our incremental thermal model is 5 times faster than that of the inverting matrix method.
文摘Floorplanning is a prominent area in the Very Large-Scale Integrated (VLSI) circuit design automation, because it influences the performance, size, yield and reliability of the VLSI chips. It is the process of estimating the positions and shapes of the modules. A high packing density, small feature size and high clock frequency make the Integrated Circuit (IC) to dissipate large amount of heat. So, in this paper, a methodology is presented to distribute the temperature of the module on the layout while simultaneously optimizing the total area and wirelength by using a hybrid Particle Swarm Optimization-Harmony Search (HPSOHS) algorithm. This hybrid algorithm employs diversification technique (PSO) to obtain global optima and intensification strategy (HS) to achieve the best solution at the local level and Modified Corner List algorithm (MCL) for floorplan representation. A thermal modelling tool called hotspot tool is integrated with the proposed algorithm to obtain the temperature at the block level. The proposed algorithm is illustrated using Microelectronics Centre of North Carolina (MCNC) benchmark circuits. The results obtained are compared with the solutions derived from other stochastic algorithms and the proposed algorithm provides better solution.
文摘We present a novel incremental algorithm for non-slicing floorplans based on the corner block list representation. The horizontal and vertical adjacency graphs are derived from the packing of the initial floorplanning results. Based on the critical path and the accumulated slack distances we define,we choose the best position for insertion and do a series of operations incrementally, such as deleting modules, adding modules, and resizing modules quickly. This incremental floorplanning algorithm has a very high speed less than 1μm,which is one of the most important measures in this research. The algorithm preserves the original good performances on area and wire length. It can also supply other tools with good physical estimates for area, wire length, and other performance guidelines.
文摘针对只有硬模块的布图规划问题,通常将其构建成组合优化模型,但求解过程时间成本高。为提高求解效率,提出了一种基于非光滑解析数学规划的布图规划算法。基于布图中器件的坐标表示,构建了一个泛化的非光滑解析数学规划模型,将不同场景下的布图规划问题的不同优化阶段处理为该泛化模型的特例,并利用共轭次梯度算法(conjugate sub-gradient algorithm,CSA)对其进行求解。针对固定轮廓布图规划问题,通过统一框架下的全局布图规划、合法化、局部优化三个阶段,实现了在固定轮廓约束下的线长优化。针对无固定轮廓约束问题,提出了带黄金分割策略的共轭次梯度算法(conjugate sub-gradient algorithm with golden section strategy,CSA_GSS),利用黄金分割策略缩小固定轮廓的面积,达到面积和线长双优化的效果。实验在GSRC测试电路上与基于B*-树表示的布图规划算法进行比较,该算法对于大规模电路在线长和时间方面均占据优势。实验结果表明,该算法能以更低的时间复杂度获得更优的线长。
文摘多电压设计是应对SoC功耗挑战的一种有效方法,但会带来线长、面积等的开销。为减少线长、芯片的空白面积及提高速度,提出了一种改进的固定边框多电压布图方法.对基于NPE(Normalized Polish Expression)表示的布图解,采用形状曲线相加算法来计算其最优的布图实现,并通过增量计算方法来减少计算NPE及多电压分配的时间.为使所得布图解满足给定的边框约束,提出了一个考虑固定边框约束的目标函数,并采用删除后插入(Insertion after Delete,IAD)算子对SA求得布图解进行后优化.实验结果表明,和已有方法相比,所提出方法在线长和空白面积率方面有较明显优势,且所有电路在不同高宽比、不同电压岛数下均实现了极低的空白面积率(<<1%).
