Quantum computers are in hot-spot with the potential to handle more complex problems than classical computers can.Realizing the quantum computation requires the universal quantum gate set {T,H,CNOT} so as to perform a...Quantum computers are in hot-spot with the potential to handle more complex problems than classical computers can.Realizing the quantum computation requires the universal quantum gate set {T,H,CNOT} so as to perform any unitary transformation with arbitrary accuracy.Here we first briefly review the Majorana fermions and then propose the realization of arbitrary two-qubit quantum gates based on chiral Majorana fermions.Elementary cells consist of a quantum anomalous Hall insulator surrounded by a topological superconductor with electric gates and quantum-dot structures,which enable the braiding operation and the partial exchange operation.After defining a qubit by four chiral Majorana fermions,the singlequbit T and H quantum gates are realized via one partial exchange operation and three braiding operations,respectively.The entangled CNOT quantum gate is performed by braiding six chiral Majorana fermions.Besides,we design a powerful device with which arbitrary two-qubit quantum gates can be realized and take the quantum Fourier transform as an example to show that several quantum operations can be performed with this space-limited device.Thus,our proposal could inspire further utilization of mobile chiral Majorana edge states for faster quantum computation.展开更多
A new T-shaped tunnel field-effect transistor(TTFET) with gate dielectric spacer(GDS) structure is proposed in this paper. To further studied the effects of GDS structure on the TTFET, detailed device characteristics ...A new T-shaped tunnel field-effect transistor(TTFET) with gate dielectric spacer(GDS) structure is proposed in this paper. To further studied the effects of GDS structure on the TTFET, detailed device characteristics such as current-voltage relationships, energy band diagrams, band-to-band tunneling(BTBT) rate and the magnitude of the electric field are investigated by using TCAD simulation. It is found that compared with conventional TTFET and TTFET with gate-drain overlap(GDO) structure, GDS-TTFET not only has the minimum ambipolar current but also can suppress the ambipolar current under a more extensive bias range. Furthermore, the analog/RF performances of GDS-TTFET are also investigated in terms of transconductance, gate-source capacitance, gate-drain capacitance, cutoff frequency, and gain bandwidth production. By inserting a low-κ spacer layer between the gate electrode and the gate dielectric, the GDS structure can effectively reduce parasitic capacitances between the gate and the source/drain, which leads to better performance in term of cutoff frequency and gain bandwidth production. Finally, the thickness of the gate dielectric spacer is optimized for better ambipolar current suppression and improved analog/RF performance.展开更多
Memristor-based neuromorphic computing shows great potential for high-speed and high-throughput signal processing applications,such as electroencephalogram(EEG)signal processing.Nonetheless,the size of one-transistor ...Memristor-based neuromorphic computing shows great potential for high-speed and high-throughput signal processing applications,such as electroencephalogram(EEG)signal processing.Nonetheless,the size of one-transistor one-resistor(1T1R)memristor arrays is limited by the non-ideality of the devices,which prevents the hardware implementation of large and complex networks.In this work,we propose the depthwise separable convolution and bidirectional gate recurrent unit(DSC-BiGRU)network,a lightweight and highly robust hybrid neural network based on 1T1R arrays that enables efficient processing of EEG signals in the temporal,frequency and spatial domains by hybridizing DSC and BiGRU blocks.The network size is reduced and the network robustness is improved while ensuring the network classification accuracy.In the simulation,the measured non-idealities of the 1T1R array are brought into the network through statistical analysis.Compared with traditional convolutional networks,the network parameters are reduced by 95%and the network classification accuracy is improved by 21%at a 95%array yield rate and 5%tolerable error.This work demonstrates that lightweight and highly robust networks based on memristor arrays hold great promise for applications that rely on low consumption and high efficiency.展开更多
基金Project supported by the National Key R&D Program of China(Grant No.2017YFA0303301)the National Natural Science Foundation of China(Grant No.11921005)+1 种基金the Strategic Priority Research Program of Chinese Academy of Sciences(Grant No.XDB28000000)Beijing Municipal Science&Technology Commission,China(Grant No.Z191100007219013)。
文摘Quantum computers are in hot-spot with the potential to handle more complex problems than classical computers can.Realizing the quantum computation requires the universal quantum gate set {T,H,CNOT} so as to perform any unitary transformation with arbitrary accuracy.Here we first briefly review the Majorana fermions and then propose the realization of arbitrary two-qubit quantum gates based on chiral Majorana fermions.Elementary cells consist of a quantum anomalous Hall insulator surrounded by a topological superconductor with electric gates and quantum-dot structures,which enable the braiding operation and the partial exchange operation.After defining a qubit by four chiral Majorana fermions,the singlequbit T and H quantum gates are realized via one partial exchange operation and three braiding operations,respectively.The entangled CNOT quantum gate is performed by braiding six chiral Majorana fermions.Besides,we design a powerful device with which arbitrary two-qubit quantum gates can be realized and take the quantum Fourier transform as an example to show that several quantum operations can be performed with this space-limited device.Thus,our proposal could inspire further utilization of mobile chiral Majorana edge states for faster quantum computation.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61306116 and 61472322)
文摘A new T-shaped tunnel field-effect transistor(TTFET) with gate dielectric spacer(GDS) structure is proposed in this paper. To further studied the effects of GDS structure on the TTFET, detailed device characteristics such as current-voltage relationships, energy band diagrams, band-to-band tunneling(BTBT) rate and the magnitude of the electric field are investigated by using TCAD simulation. It is found that compared with conventional TTFET and TTFET with gate-drain overlap(GDO) structure, GDS-TTFET not only has the minimum ambipolar current but also can suppress the ambipolar current under a more extensive bias range. Furthermore, the analog/RF performances of GDS-TTFET are also investigated in terms of transconductance, gate-source capacitance, gate-drain capacitance, cutoff frequency, and gain bandwidth production. By inserting a low-κ spacer layer between the gate electrode and the gate dielectric, the GDS structure can effectively reduce parasitic capacitances between the gate and the source/drain, which leads to better performance in term of cutoff frequency and gain bandwidth production. Finally, the thickness of the gate dielectric spacer is optimized for better ambipolar current suppression and improved analog/RF performance.
基金Project supported by the National Key Research and Development Program of China(Grant No.2019YFB2205102)the National Natural Science Foundation of China(Grant Nos.61974164,62074166,61804181,62004219,62004220,and 62104256).
文摘Memristor-based neuromorphic computing shows great potential for high-speed and high-throughput signal processing applications,such as electroencephalogram(EEG)signal processing.Nonetheless,the size of one-transistor one-resistor(1T1R)memristor arrays is limited by the non-ideality of the devices,which prevents the hardware implementation of large and complex networks.In this work,we propose the depthwise separable convolution and bidirectional gate recurrent unit(DSC-BiGRU)network,a lightweight and highly robust hybrid neural network based on 1T1R arrays that enables efficient processing of EEG signals in the temporal,frequency and spatial domains by hybridizing DSC and BiGRU blocks.The network size is reduced and the network robustness is improved while ensuring the network classification accuracy.In the simulation,the measured non-idealities of the 1T1R array are brought into the network through statistical analysis.Compared with traditional convolutional networks,the network parameters are reduced by 95%and the network classification accuracy is improved by 21%at a 95%array yield rate and 5%tolerable error.This work demonstrates that lightweight and highly robust networks based on memristor arrays hold great promise for applications that rely on low consumption and high efficiency.
