The problems existing in the binary logic system and the advantages of multiple-valued logic (MVL) are introduced. A literal circuit with three-track-output structure is created based on resonant tunneling diodes (RTD...The problems existing in the binary logic system and the advantages of multiple-valued logic (MVL) are introduced. A literal circuit with three-track-output structure is created based on resonant tunneling diodes (RTDs) and it has the most basic memory function. A ternary RTD D flip-flop with pre-set and pre-reset functions is also designed, the key module of which is the RTD literal circuit. Two types of output structure of the ternary RTD D flip-flop are optional: one is three-track and the other is single-track; these two structures can be transformed conveniently by merely adding tri-valued RTD NAND, NOR, and inverter units after the three-track output. The design is verified by simulation. Ternary flip-flop consists of an RTD literal circuit and it not only is easy to understand and implement but also provides a solution for the algebraic interface between the multiple-valued logic and the binary logic. The method can also be used for design of other types of multiple-valued RTD flip-flop circuits.展开更多
According to the next-state equations of various ternary flip-flops(tri-flop),whichare based upon ternary modular algebra,various ternary flip-flops are implemented by usinguniversal-logic-modules,U_hs.Based on it,ter...According to the next-state equations of various ternary flip-flops(tri-flop),whichare based upon ternary modular algebra,various ternary flip-flops are implemented by usinguniversal-logic-modules,U_hs.Based on it,ternary sequential circuits are implemented by usingarray of universal-logic-modules,U_hs.展开更多
Recent digital applications will require highly efficient and high-speed gadgets and it is related to the minimum delay and power consumption.The proposed work deals with a low-power clock pulsed data flip-flop(D flip...Recent digital applications will require highly efficient and high-speed gadgets and it is related to the minimum delay and power consumption.The proposed work deals with a low-power clock pulsed data flip-flop(D flip-flop)using a transmission gate.To accomplish a power-efficient pulsed D flip-flop,clock gating is proposed.The gated clock reduces the unnecessary switching of the transistors in the circuit and thus reduces the dynamic power consumption.The clock gating approach is employed by using an AND gate to disrupt the clock input to the circuit as per the control signal called Enable.Due to this process,the clock gets turned off to reduce power consumption when there is no change in the output.The proposed transmission gate-based pulsed D flip-flop’s performance with clock gating and without clock gating circuit is analyzed.The proposed pulsed D flip-flop power consumption is 1.586μw less than the without clock gated flip-flop.Also,the authors have designed a 3-bit serial-in and parallel-out shift register using the proposed D flip-flop and analyzed the performance.Tanner Electronic Design Automation tool is used to simulate all the circuits with 45 nm technology.展开更多
For the conventional single-ended eFuse cell, sensing failures can occur due to a variation of a post-program eFuse resistance during the data retention time and a relatively high program resistance of several kilo oh...For the conventional single-ended eFuse cell, sensing failures can occur due to a variation of a post-program eFuse resistance during the data retention time and a relatively high program resistance of several kilo ohms. A differential paired eFuse cell is designed which is about half the size smaller in sensing resistance of a programmed eFuse link than the conventional single-ended eFuse cell. Also, a sensing circuit of sense amplifier is proposed, based on D flip-flop structure to implement a simple sensing circuit. Furthermore, a sensing margin test circuit is proposed with variable pull-up loads out of consideration for resistance variation of a programmed eFuse. When an 8 bit eFuse OTP IP is designed with 0.18 ~tm standard CMOS logic of TSMC, the layout dimensions are 229.04 μm ×100.15μm. All the chips function successfully when 20 test chips are tested with a program voltage of 4.2 V.展开更多
Now a days,MOS Current Mode Logic(MCML)has emerged as a better alternative to Complementary Metal Oxide Semiconductor(CMOS)logic in digital circuits.Recent works have only traditional logic gates that have issues with...Now a days,MOS Current Mode Logic(MCML)has emerged as a better alternative to Complementary Metal Oxide Semiconductor(CMOS)logic in digital circuits.Recent works have only traditional logic gates that have issues with information loss.Reversible logic is incorporated with MOS Current Mode Logic(MCML)in this proposed work to solve this problem,which is used for multiplier design,D Flip-Flop(DFF)and register.The minimization of power and area is the main aim of the work.In reversible logic,the count of outputs and inputs is retained as the same value for creating one-to-one mapping.A unique output vector set can be generated for each input vector set and information loss is also prevented.In reversible MCML based multiplier,reversible logic full adder is utilized to minimize the area and power.D flip-flops based on reversible MCML are often designed to store information that is then combined to form a reversible MCML based register.The proposed reversible MCML multiplier attains average power of 0.683 mW,Reversible MCML based DFF achieves 0.56μW and Reversible MCML based 8-bit register attains 04.04μW.The result shows that the proposed Reversible MCML based multiplier,Reversible MCML based D flip-flop and ReversibleMCML based register achieves better performance in terms of current,power dissipation,average power and area.展开更多
A literal circuit with a three-track-output structure is presented based on resonant tunneling diodes(RTDs).It can be transformed conveniently into a single-track-output structure according to the definition and prope...A literal circuit with a three-track-output structure is presented based on resonant tunneling diodes(RTDs).It can be transformed conveniently into a single-track-output structure according to the definition and properties of the literal operation.A ternary resonant tunneling JK flip-flop is created based on the RTD literal circuit and the module-3 operation,and the JK flip-flop also has two optional types of output structure.The design of the ternary RTD JK flip-flop is verified by simulation.The RTD literal circuit is the key design component for achieving various types of multi-valued logic(MVL) flip-flops.It can be converted into ternary D and JK flip-flops,and the ternary JK flip-flop can also be converted simply and conveniently into ternary D and ternary T flip-flops when the input signals satisfy certain logical relationships.All these types of flip-flops can be realized using the traditional Karnaugh maps combined with the literal and module-3 operations.This approach offers a novel design method for MVL resonant tunneling flip-flop circuits.展开更多
In recent years effort has been made in overcorning an obstacle for multivalued logic to be practically used — the lack of suitable storage elements. Refs. [1—3] proposed the design of master-slave JKL type, T type,...In recent years effort has been made in overcorning an obstacle for multivalued logic to be practically used — the lack of suitable storage elements. Refs. [1—3] proposed the design of master-slave JKL type, T type, D type tri-flops and edge-triggered D type, T展开更多
The usage of multiple-valued logic is not so common as binary logic in the electric science and technology. One reason is that it lacks the proper memory element which is not too complicated. Ref. [2] which studied th...The usage of multiple-valued logic is not so common as binary logic in the electric science and technology. One reason is that it lacks the proper memory element which is not too complicated. Ref. [2] which studied the ternary masterslave flip-flop with three-rail output solved this problem. A sort of ternary edgetriggered D flip-flop corresponding to Ref. [2] has been designed in Ref. (3)展开更多
The stability constants of PdAB ternary complexes were determined by potentionmetric pH titration at 25℃,I=0.1mol/l KNO3,whereA=2,2′-bipyridy1-3,3′-dicarboxylicacid,B=Alanine,3,5-Dibr-tyrosine and 3,5-DiI-tyrosine....The stability constants of PdAB ternary complexes were determined by potentionmetric pH titration at 25℃,I=0.1mol/l KNO3,whereA=2,2′-bipyridy1-3,3′-dicarboxylicacid,B=Alanine,3,5-Dibr-tyrosine and 3,5-DiI-tyrosine.The binary complexes stability constants have also been determined at the same conditions.And compared with alanine,tyrosine system,the possible reasons that lead to extra stability of ternary complexes were discussed from the viewpoint of aromatic ring stacking,d-pπbond or hydrogen-bond.展开更多
Manganese phosphorous selenium(MnPSe_(3)),as a representative of layered metal phosphorus trichalcogenides(MPTs),has gained significant attention due to its direct bandgap,high carrier mobility,large absorption coeffi...Manganese phosphorous selenium(MnPSe_(3)),as a representative of layered metal phosphorus trichalcogenides(MPTs),has gained significant attention due to its direct bandgap,high carrier mobility,large absorption coefficient,which indicate great potential in photoelectric application.Herein,high-quality two-dimensional(2D)MnPSe_(3) flakes were mechanically exfoliated from the corresponding bulk crystals synthesized by chemical vapor transport(CVT)methods.The systematic investigation was applied to the lattice vibrations of MnPSe_(3) via angle-resolved polarized Raman spectroscopy(ARPRS),and the Raman vibration modes were determined based on Raman selection rules and crystal symmetry.Impressively,the photodetectors based on 2D MnPSe_(3) flakes exhibit excellent photoresponse to the ultraviolet light with a responsivity up to 22.7 A W^(-1) and a detectivity of 2.4×10^(11) Jones.The high performance in the ultraviolet range signifies that 2D MnPSe_(3) is expected to be a powerful candidate for future ultraviolet photodetection.展开更多
Depletion-mode and enhancement-mode AlGaN/GaN HEMTs using fluorine plasma treatment were integrated on one wafer.Direct-coupled FET logic circuits,such as an E/D HEMT inverter,NAND gate and D flip-flop,were fabricated...Depletion-mode and enhancement-mode AlGaN/GaN HEMTs using fluorine plasma treatment were integrated on one wafer.Direct-coupled FET logic circuits,such as an E/D HEMT inverter,NAND gate and D flip-flop,were fabricated on an AlGaN/GaN heterostructure.The D flip-flop and NAND gate are demonstrated in a GaN system for the first time.The dual-gate AlGaN/GaN E-HEMT substitutes two single-gate E-HEMTs for simplifying the NAND gate and shrinking the area,integrating with a conventional AlGaN/GaN D-HEMT and demonstrating a NAND gate.E/D-mode D flip-flop was fabricated by integrating the inverters and the NAND gate on the AlGaN/GaN heterostructure.At a supply voltage of 2 V,the E/D inverter shows an output logic swing of 1.7 V,a logic-low noise margin of 0.49 V and a logic-high noise margin of 0.83 V.The NAND gate and D flip-flop showed correct logic function demonstrating promising potential for GaN-based digital ICs.展开更多
Two-dimensional(2D) ternary materials have sprung up in a broad variety of optoelectronic applications due to their robust degree of freedom to design the physical properties of the materials through adjusting the sto...Two-dimensional(2D) ternary materials have sprung up in a broad variety of optoelectronic applications due to their robust degree of freedom to design the physical properties of the materials through adjusting the stoichiometric ratio. However, the controlled growth of high-quality 2D ternary materials with good chemical stoichiometry remains challenging, which severely impedes their further development and future device applications. Herein, we synthesize ternary Bi_(2)Te_(2)Se(BTS) flakes with a thickness down to 4 nm and a lateral dimension about 60 μm by an atmospheric-pressure solid source thermal evaporation method on a mica substrate. The phonon vibration and electrical transportation of 2D BTS are respectively investigated by temperature-dependent Raman spectrum and conductivity measurements. Furthermore, the photodetector based on 2D BTS exhibits excellent performance with a high light on/off ratio of 1300(365 nm), a wide spectral response range from 365 to 980 nm, and an ultra-fast response speed up to 2 μs. In addition, its electrical and photoelectric properties can be modulated by the gate voltage, offering an improved infrared responsivity to 2.74 A W^(-1) and an on/off ratio of 2266 under 980 nm. This work introduces an effective approach to obtain 2D BTS flakes and demonstrates their excellent prospects in optoelectronics.展开更多
With the emergence of non-fullerene acceptors(NFAs),the power conversion efficiencies(PCEs)of allsmall-molecule organic solar cells(ASM-OSCs)have been significantly improved.However,due to the strong crystallinities o...With the emergence of non-fullerene acceptors(NFAs),the power conversion efficiencies(PCEs)of allsmall-molecule organic solar cells(ASM-OSCs)have been significantly improved.However,due to the strong crystallinities of small molecules,it is much more challenging to obtain the ideal phase separation morphology and efficient charge transport pathways for ASM-OSCs.Here,a high-efficiency ternary ASMOSC has been successfully constructed based on H11/IDIC-4 F system by introduction of IDIC with a similar backbone as IDIC-4F but weak crystallinity.Notably,the addition of IDIC has effectively suppressed large-scale phase aggregation and optimized the morphology of the blend film.More importantly,the molecular orientation has also been significantly adjusted,and a mixed face-on and edge-on orientation has formed,thus establishing a more favorable three-dimensional(3D)charge pathways in the active layer.With these improvements,the enhanced short-circuit current density(JSC)and fill factor(FF)of the ternary system have been achieved.In addition,because of the high lowest unoccupied molecular orbital(LUMO)energy level of IDIC as well as the alloyed structure of the IDIC and IDIC-4F,the promoted open circuit voltage(VOC)of the ternary system has also been realized.展开更多
文摘The problems existing in the binary logic system and the advantages of multiple-valued logic (MVL) are introduced. A literal circuit with three-track-output structure is created based on resonant tunneling diodes (RTDs) and it has the most basic memory function. A ternary RTD D flip-flop with pre-set and pre-reset functions is also designed, the key module of which is the RTD literal circuit. Two types of output structure of the ternary RTD D flip-flop are optional: one is three-track and the other is single-track; these two structures can be transformed conveniently by merely adding tri-valued RTD NAND, NOR, and inverter units after the three-track output. The design is verified by simulation. Ternary flip-flop consists of an RTD literal circuit and it not only is easy to understand and implement but also provides a solution for the algebraic interface between the multiple-valued logic and the binary logic. The method can also be used for design of other types of multiple-valued RTD flip-flop circuits.
基金Supported by the National Natural Science Foundation of Zhejiang Province,China.
文摘According to the next-state equations of various ternary flip-flops(tri-flop),whichare based upon ternary modular algebra,various ternary flip-flops are implemented by usinguniversal-logic-modules,U_hs.Based on it,ternary sequential circuits are implemented by usingarray of universal-logic-modules,U_hs.
文摘Recent digital applications will require highly efficient and high-speed gadgets and it is related to the minimum delay and power consumption.The proposed work deals with a low-power clock pulsed data flip-flop(D flip-flop)using a transmission gate.To accomplish a power-efficient pulsed D flip-flop,clock gating is proposed.The gated clock reduces the unnecessary switching of the transistors in the circuit and thus reduces the dynamic power consumption.The clock gating approach is employed by using an AND gate to disrupt the clock input to the circuit as per the control signal called Enable.Due to this process,the clock gets turned off to reduce power consumption when there is no change in the output.The proposed transmission gate-based pulsed D flip-flop’s performance with clock gating and without clock gating circuit is analyzed.The proposed pulsed D flip-flop power consumption is 1.586μw less than the without clock gated flip-flop.Also,the authors have designed a 3-bit serial-in and parallel-out shift register using the proposed D flip-flop and analyzed the performance.Tanner Electronic Design Automation tool is used to simulate all the circuits with 45 nm technology.
文摘For the conventional single-ended eFuse cell, sensing failures can occur due to a variation of a post-program eFuse resistance during the data retention time and a relatively high program resistance of several kilo ohms. A differential paired eFuse cell is designed which is about half the size smaller in sensing resistance of a programmed eFuse link than the conventional single-ended eFuse cell. Also, a sensing circuit of sense amplifier is proposed, based on D flip-flop structure to implement a simple sensing circuit. Furthermore, a sensing margin test circuit is proposed with variable pull-up loads out of consideration for resistance variation of a programmed eFuse. When an 8 bit eFuse OTP IP is designed with 0.18 ~tm standard CMOS logic of TSMC, the layout dimensions are 229.04 μm ×100.15μm. All the chips function successfully when 20 test chips are tested with a program voltage of 4.2 V.
文摘Now a days,MOS Current Mode Logic(MCML)has emerged as a better alternative to Complementary Metal Oxide Semiconductor(CMOS)logic in digital circuits.Recent works have only traditional logic gates that have issues with information loss.Reversible logic is incorporated with MOS Current Mode Logic(MCML)in this proposed work to solve this problem,which is used for multiplier design,D Flip-Flop(DFF)and register.The minimization of power and area is the main aim of the work.In reversible logic,the count of outputs and inputs is retained as the same value for creating one-to-one mapping.A unique output vector set can be generated for each input vector set and information loss is also prevented.In reversible MCML based multiplier,reversible logic full adder is utilized to minimize the area and power.D flip-flops based on reversible MCML are often designed to store information that is then combined to form a reversible MCML based register.The proposed reversible MCML multiplier attains average power of 0.683 mW,Reversible MCML based DFF achieves 0.56μW and Reversible MCML based 8-bit register attains 04.04μW.The result shows that the proposed Reversible MCML based multiplier,Reversible MCML based D flip-flop and ReversibleMCML based register achieves better performance in terms of current,power dissipation,average power and area.
文摘A literal circuit with a three-track-output structure is presented based on resonant tunneling diodes(RTDs).It can be transformed conveniently into a single-track-output structure according to the definition and properties of the literal operation.A ternary resonant tunneling JK flip-flop is created based on the RTD literal circuit and the module-3 operation,and the JK flip-flop also has two optional types of output structure.The design of the ternary RTD JK flip-flop is verified by simulation.The RTD literal circuit is the key design component for achieving various types of multi-valued logic(MVL) flip-flops.It can be converted into ternary D and JK flip-flops,and the ternary JK flip-flop can also be converted simply and conveniently into ternary D and ternary T flip-flops when the input signals satisfy certain logical relationships.All these types of flip-flops can be realized using the traditional Karnaugh maps combined with the literal and module-3 operations.This approach offers a novel design method for MVL resonant tunneling flip-flop circuits.
基金Project supported by the National Natural Science Foundation of China
文摘In recent years effort has been made in overcorning an obstacle for multivalued logic to be practically used — the lack of suitable storage elements. Refs. [1—3] proposed the design of master-slave JKL type, T type, D type tri-flops and edge-triggered D type, T
文摘The usage of multiple-valued logic is not so common as binary logic in the electric science and technology. One reason is that it lacks the proper memory element which is not too complicated. Ref. [2] which studied the ternary masterslave flip-flop with three-rail output solved this problem. A sort of ternary edgetriggered D flip-flop corresponding to Ref. [2] has been designed in Ref. (3)
文摘The stability constants of PdAB ternary complexes were determined by potentionmetric pH titration at 25℃,I=0.1mol/l KNO3,whereA=2,2′-bipyridy1-3,3′-dicarboxylicacid,B=Alanine,3,5-Dibr-tyrosine and 3,5-DiI-tyrosine.The binary complexes stability constants have also been determined at the same conditions.And compared with alanine,tyrosine system,the possible reasons that lead to extra stability of ternary complexes were discussed from the viewpoint of aromatic ring stacking,d-pπbond or hydrogen-bond.
基金supported by the National Natural Science Foundation of China(21825103)Hubei Provincial Natural Science Foundation(2019CFA002)+1 种基金the Fundamental Research Funds for the Central Universities(2019kfyXMBZ018)the support from the Analytical and Testing Center of Huazhong University of Science and Technology。
文摘Manganese phosphorous selenium(MnPSe_(3)),as a representative of layered metal phosphorus trichalcogenides(MPTs),has gained significant attention due to its direct bandgap,high carrier mobility,large absorption coefficient,which indicate great potential in photoelectric application.Herein,high-quality two-dimensional(2D)MnPSe_(3) flakes were mechanically exfoliated from the corresponding bulk crystals synthesized by chemical vapor transport(CVT)methods.The systematic investigation was applied to the lattice vibrations of MnPSe_(3) via angle-resolved polarized Raman spectroscopy(ARPRS),and the Raman vibration modes were determined based on Raman selection rules and crystal symmetry.Impressively,the photodetectors based on 2D MnPSe_(3) flakes exhibit excellent photoresponse to the ultraviolet light with a responsivity up to 22.7 A W^(-1) and a detectivity of 2.4×10^(11) Jones.The high performance in the ultraviolet range signifies that 2D MnPSe_(3) is expected to be a powerful candidate for future ultraviolet photodetection.
基金Project supported by the National Natural Science Foundation of China(No60736033)
文摘Depletion-mode and enhancement-mode AlGaN/GaN HEMTs using fluorine plasma treatment were integrated on one wafer.Direct-coupled FET logic circuits,such as an E/D HEMT inverter,NAND gate and D flip-flop,were fabricated on an AlGaN/GaN heterostructure.The D flip-flop and NAND gate are demonstrated in a GaN system for the first time.The dual-gate AlGaN/GaN E-HEMT substitutes two single-gate E-HEMTs for simplifying the NAND gate and shrinking the area,integrating with a conventional AlGaN/GaN D-HEMT and demonstrating a NAND gate.E/D-mode D flip-flop was fabricated by integrating the inverters and the NAND gate on the AlGaN/GaN heterostructure.At a supply voltage of 2 V,the E/D inverter shows an output logic swing of 1.7 V,a logic-low noise margin of 0.49 V and a logic-high noise margin of 0.83 V.The NAND gate and D flip-flop showed correct logic function demonstrating promising potential for GaN-based digital ICs.
基金supported by the National Natural Science Foundation of China (21825103)Hubei Provincial Natural Science Foundation of China (2019CFA002)the Fundamental Research Funds for the Central Universities (2019kfy XMBZ018)。
文摘Two-dimensional(2D) ternary materials have sprung up in a broad variety of optoelectronic applications due to their robust degree of freedom to design the physical properties of the materials through adjusting the stoichiometric ratio. However, the controlled growth of high-quality 2D ternary materials with good chemical stoichiometry remains challenging, which severely impedes their further development and future device applications. Herein, we synthesize ternary Bi_(2)Te_(2)Se(BTS) flakes with a thickness down to 4 nm and a lateral dimension about 60 μm by an atmospheric-pressure solid source thermal evaporation method on a mica substrate. The phonon vibration and electrical transportation of 2D BTS are respectively investigated by temperature-dependent Raman spectrum and conductivity measurements. Furthermore, the photodetector based on 2D BTS exhibits excellent performance with a high light on/off ratio of 1300(365 nm), a wide spectral response range from 365 to 980 nm, and an ultra-fast response speed up to 2 μs. In addition, its electrical and photoelectric properties can be modulated by the gate voltage, offering an improved infrared responsivity to 2.74 A W^(-1) and an on/off ratio of 2266 under 980 nm. This work introduces an effective approach to obtain 2D BTS flakes and demonstrates their excellent prospects in optoelectronics.
基金supported financially by National Natural Science Foundation of China(Nos.21822503,51973043,51822301 and 91963126)the Ministry of Science and Technology of the People’s Republic of China(Nos.2016YFA0200700,2017YFA0206600)+4 种基金the Strategic Priority Research Program of the Chinese Academy of Sciences(No.XDB36020000)Beijing National Laboratory for Molecular Sciences(No.BNLMS201907)Youth Innovation Promotion AssociationK.C.Wong Education Foundationthe CAS Pioneer Hundred Talents Program。
文摘With the emergence of non-fullerene acceptors(NFAs),the power conversion efficiencies(PCEs)of allsmall-molecule organic solar cells(ASM-OSCs)have been significantly improved.However,due to the strong crystallinities of small molecules,it is much more challenging to obtain the ideal phase separation morphology and efficient charge transport pathways for ASM-OSCs.Here,a high-efficiency ternary ASMOSC has been successfully constructed based on H11/IDIC-4 F system by introduction of IDIC with a similar backbone as IDIC-4F but weak crystallinity.Notably,the addition of IDIC has effectively suppressed large-scale phase aggregation and optimized the morphology of the blend film.More importantly,the molecular orientation has also been significantly adjusted,and a mixed face-on and edge-on orientation has formed,thus establishing a more favorable three-dimensional(3D)charge pathways in the active layer.With these improvements,the enhanced short-circuit current density(JSC)and fill factor(FF)of the ternary system have been achieved.In addition,because of the high lowest unoccupied molecular orbital(LUMO)energy level of IDIC as well as the alloyed structure of the IDIC and IDIC-4F,the promoted open circuit voltage(VOC)of the ternary system has also been realized.
