Power dissipation, speed and stability are the most important parameters for multiple-valued SRAM design. To reduce the power consumption and further improve the performance of the ternary SRAM cell, we propose a low ...Power dissipation, speed and stability are the most important parameters for multiple-valued SRAM design. To reduce the power consumption and further improve the performance of the ternary SRAM cell, we propose a low standby-power fast ternary SRAM cell based on carbon nanotube field effect transistors(CNFETs).The performance is simulated in terms of three criteria including standby-power, delay(write and read) and stability(RSNM). Compared to the novel ternary SRAM cell, our results show that the average standby-power, write and read delay of the proposed cell are reduced by 78.1%, 39.6% and 58.2%, respectively. In addition, the RSNM under process variations is 2.01× and 1.95× of the conventional and novel ternary SRAM cells, respectively.展开更多
Based on multi-valued logic,adiabatic circuits and the structure of ternary static random access memory （SRAM）,a design scheme of a novel ternary clocked adiabatic SRAM is presented.The scheme adopts bootstrapped NM...Based on multi-valued logic,adiabatic circuits and the structure of ternary static random access memory （SRAM）,a design scheme of a novel ternary clocked adiabatic SRAM is presented.The scheme adopts bootstrapped NMOS transistors,and an address decoder,a storage cell and a sense amplifier are charged and discharged in the adiabatic way,so the charges stored in the large switch capacitance of word lines,bit lines and the address decoder can be effectively restored to achieve energy recovery during reading and writing of ternary signals.The PSPICE simulation results indicate that the ternary clocked adiabatic SRAM has a correct logic function and low power consumption.Compared with ternary conventional SRAM,the average power consumption of the ternary adiabatic SRAM saves up to 68%in the same conditions.展开更多
基金supported by the National Natural Science Foundation of China(Nos.61474068,61234002,61404076)the S&T Plan of Zhejiang Provincial Science and Technology Department(No.2016C31078)the K.C.Wong Magna Fund in Ningbo University,China
文摘Power dissipation, speed and stability are the most important parameters for multiple-valued SRAM design. To reduce the power consumption and further improve the performance of the ternary SRAM cell, we propose a low standby-power fast ternary SRAM cell based on carbon nanotube field effect transistors(CNFETs).The performance is simulated in terms of three criteria including standby-power, delay(write and read) and stability(RSNM). Compared to the novel ternary SRAM cell, our results show that the average standby-power, write and read delay of the proposed cell are reduced by 78.1%, 39.6% and 58.2%, respectively. In addition, the RSNM under process variations is 2.01× and 1.95× of the conventional and novel ternary SRAM cells, respectively.
基金Project supported by the National Natural Science Foundation of China(No.61076032)the Key Project of Zhejiang Provincial Natural Science of China(No.Z1111219)the K.C.Wong Magna Fund in Ningbo University,China
文摘Based on multi-valued logic,adiabatic circuits and the structure of ternary static random access memory （SRAM）,a design scheme of a novel ternary clocked adiabatic SRAM is presented.The scheme adopts bootstrapped NMOS transistors,and an address decoder,a storage cell and a sense amplifier are charged and discharged in the adiabatic way,so the charges stored in the large switch capacitance of word lines,bit lines and the address decoder can be effectively restored to achieve energy recovery during reading and writing of ternary signals.The PSPICE simulation results indicate that the ternary clocked adiabatic SRAM has a correct logic function and low power consumption.Compared with ternary conventional SRAM,the average power consumption of the ternary adiabatic SRAM saves up to 68%in the same conditions.
