A Radial Stub Test Circuit for Microwave Power Devices

With the principles of microwave circuits and semiconductor device physics, two microwave power device test circuits combined with a test fixture are designed and simulated, whose properties are evaluated by a parameter network analyzer within the frequency range from 3 to 8GHz. The simulation and experimental results verify that the test circuit with a radial stub is better than that without. As an example, a C-band AlGaN/GaN HEMT microwave power device is tested with the designed circuit and fixture. With a 5.4GHz microwave input signal,the maximum gain is 8.75dB,and the maximum output power is 33.2dBm.

Investigation into Equivalency of Synthetic Test Circuit Used for Operational Tests of Thyristor Valves for UHVDC

With the growth of capacity of high voltage direct current(HVDC) transmission lines,the ratings of thyristor valves,which are one of the most critical equipments,are getting higher and higher.Verification of performance of thyristor valves particularly designed for HVDC project plays an important role in the handover of products between the manufacturer and the client.Conventional test facilities based on philosophy of direct test cannot meet the requirements for modern thyristor valves.New test facilities with high ratings are necessarily built based on philosophy of synthetic test.Over the conventional direct test circuit,the later is an economical and feasible solution with less financial investment and higher test capability.However,the equivalency between the synthetic test and the direct test should be analyzed technically in order to make sure that the condition of verification test in a synthetic test circuit should satisfy the actual operation condition of thyristor valves existing in a real HVDC project,just as in a direct test circuit.Equivalency analysis is focused in this paper,covering the scope of thyristor valves' steady state,and transient state.On the basis of the results achieved,a synthetic test circuit of 6 500 A/50 kV for operational tests of thyristor valves used for up to UHVDC project has newly been set up and already put into service in Xi'an High Voltage Apparatus Research Institute Co.,Ltd.(XIHARI),China.Some of the results have been adopted also by a new national standard of China.

The Transformer Short-Circuit Test and the High Power Laboratory in China-the Past,Present,and Future

We review the short-circuit testing of distribution and power transformers, and include a list of 110-220kV power transformers tested up to February 2002.

Influence of Tilted Angle on Effective Linear Energy Transfer in Single Event Effect Tests for Integrated Circuits at 130 nm Technology Node

A heavy-ion irradiation experiment is studied in digital storage cells with different design approaches in 130？nm CMOS bulk Si and silicon-on-insulator （SOI） technologies. The effectiveness of linear energy transfer （LET） with a tilted ion beam at the 130？nm technology node is obtained. Tests of tilted angles θ=0 ° , 30 ° and 60 ° with respect to the normal direction are performed under heavy-ion Kr with certain power whose LET is about 40？MeVcm 2 /mg at normal incidence. Error numbers in D flip-flop chains are used to determine their upset sensitivity at different incidence angles. It is indicated that the effective LETs for SOI and bulk Si are not exactly in inverse proportion to cosθ , furthermore the effective LET for SOI is more closely in inverse proportion to cosθ compared to bulk Si, which are also the well known behavior. It is interesting that, if we design the sample in the dual interlocked storage cell approach, the effective LET in bulk Si will look like inversely proportional to cosθ very well, which is also specifically explained.

Test system of the front-end readout for an application-specific integrated circuit for the water Cherenkov detector array at the large high-altitude air shower observatory

The water Cherenkov detector array(WCDA) is an important part of the large high-altitude air shower observatory(LHAASO),which is in a research and development phase.The central scientific goal of LHAASO is to explore the origin of high-energy cosmic rays of the universe and to push forward the frontier of new physics.To simplify the WCDA's readout electronics,a prototype of a front-end readout for an application-specific integrated circuit(ASIC) is designed based on the timeover-threshold method to achieve charge-to-time conversion.High-precision time measurement and charge measurement are necessary over a full dynamic range[1-4000photoelectrons(P.E.)].To evaluate the performance of this ASIC,a test system is designed that includes the front-end ASIC test module,digitization module,and test software.The first module needs to be customized for different ASIC versions,whereas the digitization module and test software are tested for general-purpose use.In the digitization module,a field programmable gate array-based time-todigital converter is designed with a bin size of 333 ps,which also integrates an inter-integrated circuit to configure the ASIC test module,and a universal serial bus interface is designed to transfer data to the remote computer.Test results indicate that the time resolution is better than 0.5 ns,and the charge resolution is better than 30%root mean square(RMS) at 1 P.E.and 3%RMS at 4000 P.E.,which are beyond the application requirements.

VST/DL Digital Circuit Testing & Analytical System

An important means for digital circuit analysis, design. maintenance and production is the IC chip test and analysis. With digital circuit application prevailing today, the automatic test and analysis of digital circuits is going to play a more important role. It can save a great deal of time and cost for the maintenance of equipment and can also provide correst analytical data for designers.

The embedded design verification test of microwave circuit modules based on specific chips

In the Paper,the author introduces an embedded design verification test based on specific chips to solve the technical problems of microwave circuit test and fault diagnosis.The author explains embedded design of microwave circuit modules and approach of hardware design and software design,and finally verifies the embedded design of microwave circuit modules based on specific chips.

Key stress extraction and equivalent test method for hybrid DC circuit breaker

Firstly, relevant stress properties of millisecond level breaking process and microsecond level commutation process of hybrid HVDC circuit breaker are studied in detail on the basis of the analysis for the application environment and topological structure and operating principles of hybrid circuit breakers, and key stress parameters in transient state process of two time dimensions are extracted. The established digital simulation circuit for PSCAD/EMTDC device-level operation of the circuit breaker has verified the stress properties of millisecond level breaking process and microsecond level commutation process. Then, equivalent test method, circuits and parameters based on LC power supply are proposed on the basis of stress extraction. Finally, the results of implemented breaking tests for complete 200 kV circuit breaker, 100 kV and 50 kV circuit breaker units, as well as single power electronic module have verified the accuracy of the simulation circuit and mathematical analysis. The result of this paper can be a guide to electrical structure and test system design of hybrid HVDC circuit breaker.

Chair's Introduction to 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis

Based on the recommendation of ICTD＇09 TPC members, this Special Issue of the Journal of Electronic Science ＆ Technology of China （JESTC） contained 22 high quality papers selected from the Proceedings of 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis （ICTD ＇09） which is fully sponsored by the IEEE Circuits and Systems Society （CASS）, and is technically co-sponsored by the University of Electronic Science and Technology of China （UESTC）, the Chinese Institute of Electronics （CIE）, the China Instrument ＆ Control Society （CIS）, and organized by UESTC.

General Consideration of Measuring System for Operational Test of Thyristor Valves of Ultra High Voltage DC Power Transmission

Thyristor valve is one of the key equipments for ultra high voltage direct current(UHVDC) power transmission projects.Before being installed on site,they need to be tested in a laboratory in order to verify their operational performance to satisfy the technical specification of project related.Test facilities for operational tests of thyristor valves are supposed to enable to undertake more severe electrical stresses than those being applied in the thyristor valves under test(test objects).On the other hand,the stresses applied into the test objects are neither higher nor lower than specified by the specification,because inappropriate stresses applied would result in incorrect evaluation of performance on the test objects,more seriously,would cuase the damage of test objects with expensive cost losing.Generally,the process of operational tests is complicated and performed in a complex synthetic test circuit(hereafter as STC),where there are a lot of sensors used for measuring,monitoring and protection on line to ensure that the test circuit functions in good condition.Therefore,the measuring systems embedded play a core role in STC,acting like "eyes".Based on the first project of building up a STC in China,experience of planning measuring systems is summarized so as to be referenced by related engineers.

TEST OF BOARD-LEVEL BOUNDARY SCAN INTEGRITY

The IEEE Standard 1149.1 boundary scan (BS) implementation provides the internal access required for testing the digital printed circuit board (PCB). However, the integrity of the boundary scan test infrastructure should be tested first to guarantee the validation of the results of the rest functional test and diagnosis. This paper describes the fault models and test principles of the BS test access port (TAP) lines on PCBs. A test algorithm with high fault coverage and short time is then presented for the PCB on which all ICs are BS ones.

基于TestStand的医疗仪器产品性能自动测试系统研制

为解决传统人工测量方式对电子医疗仪器产品板卡性能检验中测量效率低、测量不准确和测量手段复杂等问题,提高生产效率和板卡的质量控制,对虚拟仪器技术以及自动测试系统技术进行了研究;研制开发了一种基于TestStand和LabVIEW的电子产品性能自动测试系统;自动测试系统通过控制TestStand引擎调用待测试板卡的测试序列实现对不同板卡的测试,测试序列是由各测量程序配置组成;设计的测试参数集中配置、项目分组测试以及测试产品目录自动生成方案,提高了系统的通用性、扩展性以及灵活性;实验和实际应用表明,该系统在应用中具有很高的测试效率和测量准确性并且操作简便。

动态水力旋流器内短路流流量的计算方法及影响分析

短路流是影响水力旋流器分离效率的重要因素,然而针对动态水力旋流器中短路流的形式和计算方法鲜有研究。本文通过数值模拟的方式对动态水力旋流器溢流管口处径向速度变化和流线分布规律,提出了一种基于数值模拟的动态水力旋流器短路流流量计算方法。将量纲为1的动态水力旋流器高灵敏度结构参数作为输入指标,以数值模拟所得的短路流率作为响应目标,通过响应曲面法建立了量纲为1的结构参数与短路流率间的计算模型。基于所建立的模型,使单管处理量为120m^(3)/h的动态水力旋流器进行结构改进,改进后短路流流量减少了59.6%,分离效率提高了10.4%,基于该方法改进的单管120m^(3)/h处理量动态水力旋流器中试样机通过了海上石油平台上的试验验证,且试验分离性能与模拟预测分离效率间的平均误差仅有4.9%。

可控换相换流阀可控关断试验研究及工程应用

高压直流可控换相换流(controllable line commutated converter,CLCC)阀采用晶闸管与绝缘栅双极晶体管(insulated gate bipolar transistor,IGBT)器件混联的方式,形成主、辅两条支路并联结构,主支路起正常通流作用,发生交流故障时由辅助支路承接主支路电流,待主支路恢复阻断后主动关断实现强迫换相,从根本上解决直流系统换相失败的难题,适用于我国多馈入直流受端电网。为等效复现可控换相换流阀稳态运行下电热应力以及交流故障期间连续强迫换相过程产生的瞬变高电压、大电流及脉冲能量,需开展阀组件可控关断试验方法研究,验证CLCC换流阀抵御换相失败能力。依托葛南直流改造工程系统仿真结果,分析了逆变侧单相接地故障下各子阀瞬变高压、大电流应力水平,提取实际工况下各子阀关键应力指标;其次,提出了多频谐振电流源、稳态高压源周期性复合试验方法,完成故障电流连续分断试验装置参数设计,实现无外部负向电压施加时桥臂可控阻断恢复能力的模拟。通过试验和仿真对比分析,验证了该试验方法的可行性及等效性,为后续不同电流等级可控换相换流阀可控关断试验提供理论和技术指导。

Circuit-field coupled finite element analysis method for an electromagnetic acoustic transducer under pulsed voltage excitation

This paper presents an analytical method for electromagnetic acoustic transducers （EMATs） under voltage excitation and considers the non-uniform distribution of the biased magnetic field. A complete model of EMATs including the non-uniform biased magnetic field, a pulsed eddy current field and the acoustic field is built up. The pulsed voltage excitation is transformed to the frequency domain by fast Fourier transformation （FFT）. In terms of the time harmonic field equations of the EMAT system, the impedances of the coils under different frequencies are calculated according to the circuit-field coupling method and Poynting＇s theorem. Then the currents under different frequencies are calculated according to Ohm＇s law and the pulsed current excitation is obtained by inverse fast Fourier transformation （IFFT）. Lastly, the sequentially coupled finite element method （FEM） is used to calculate the Lorentz force in the EMATs under the current excitation. An actual EMAT with a two-layer two-bundle printed circuit board （PCB） coil, a rectangular permanent magnet and an aluminium specimen is analysed. The coil impedances and the pulsed current are calculated and compared with the experimental results. Their agreement verified the validity of the proposed method. Furthermore, the influences of lift-off distances and the non-uniform static magnetic field on the Lorentz force under pulsed voltage excitation are studied.

基于TestStand的自动测试程序开发及应用

随着芯片集成度和PCB电路板布线密度的不断提高,电路板的功能和结构日益复杂,当前公司的电路板测试系统不能满足公司生产电路板的测试需求。为解决本公司生产部门关于电路板测试环节对操作人员知识和技能要求高、测试时间长、人工成本高、测试不全面不准确等常见问题,研发了基于TestStand的自动测试程序,完成了硬件平台的搭建以及程序的试验验证。实际应用表明,本测试程序能够可靠稳定地完成电路板测试任务,而且操作系统简单、兼容性高、灵活性好,对操作人员的技术水平要求低,有效提升了电路板产品的测试精度与测试效率,同时也对本公司产品开拓市场起到了至关重要的作用。

基于LabVIEW与TestStand的通用板卡自动测试系统

随着电路板复杂程度及功能的增加,人工测试已经无法满足大规模板卡产品化测试的需求。针对板卡类型多、测试信号种类多、功能复杂的场合人工测试存在效率低、可靠性差等问题,提出了一种基于Lab VIEW与Test Stand的通用板卡自动测试系统设计方案,完成了硬件平台的搭建以及相关软件的设计。该系统可对多种类型电路板卡进行自动测试,具有可靠性高、二次开发周期短、人机界面友好、测试结果自动存储等特点,实践证明使用该测试系统可大大提高电路板的测试效率。

Simulation and Experimental Analysis of Arc Motion Characteristics in Air Circuit Breaker

In this paper, to simulate the arc motion in an air circuit breaker （ACB）, a three- dimensional magneto-hydrodynamic （MHD） model is developed, considering the influence of ther- mal radiation, the change of physical parameters of arc plasma and the nonlinear characteristic of ferromagnetic material. The distributions of pressure, temperature, gas flow and current density of arc plasma in the arc region are calculated. The simulation results show some phenomena which discourage arc interruption, such as back commutation and arc burning at the back of the splitter plate. To verify the simulation model, the arc motion is studied experimentally. The influences of the material and position of the innermost barrier plate are analyzed mainly. It proved that the model developed in this paper can efficiently simulate the arc motion. The results indicate that the insulation barrier plate close to the top of the splitter plate is conducive to the arc splitting, which leads to the significant increase of the arc voltage, so it is better for arc interruption. The research can provide methods and references to the optimization of ACB design.

Test Vector Optimization Using Pocofan-Poframe Partitionin

This paper presents an automated POCOFAN-POFRAME algorithm thatpartitions large combinational digital VLSI circuits for pseudo exhaustive testing. In thispaper, a simulation framework and partitioning technique are presented to guide VLSIcircuits to work under with fewer test vectors in order to reduce testing time and todevelop VLSI circuit designs. This framework utilizes two methods of partitioningPrimary Output Cone Fanout Partitioning (POCOFAN) and POFRAME partitioning todetermine number of test vectors in the circuit. The key role of partitioning is to identifyreconvergent fanout branch pairs and the optimal value of primary input node N andfanout F partitioning using I-PIFAN algorithm. The number of reconvergent fanout andits locations are critical for testing of VLSI circuits and design for testability. Hence, theirselection is crucial in order to optimize system performance and reliability. In the presentwork, the design constraints of the partitioned circuit considered for optimizationincludes critical path delay and test time. POCOFAN-POFRAME algorithm uses theparameters with optimal values of circuits maximum primary input cone size (N) andminimum fan-out value (F) to determine the number of test vectors, number of partitionsand its locations. The ISCAS’85 benchmark circuits have been successfully partitioned,the test results of C499 shows 45% reduction in the test vectors and the experimentalresults are compared with other partitioning methods, our algorithm makes fewer testvectors.

Study on Test Compaction in High-Level Automatic Test Pattern Generation (ATPG) Platform

Advancements in semiconductor technology are making gate-level test generation more challenging. This is because a large amount of detailed structural information must be processed in the search process of automatic test pattern generation (ATPG). In addition, ATPG needs to deal with new defects caused by process variation when IC is shrinking. To reduce the computation effort of ATPG, test generation could be started earlier at higher abstraction level, which is in line with top-down design methodology that has become more popular nowadays. In this research, we employ Chen’s high-level fault model in the high-level ATPG. Besides shorter ATPG time as shown in many previous works, our study showed that high-level ATPG also contributes to test compaction. This is because most of the high-level faults correlate with the gate-level collapsed faults especially at input/output of the modules in a circuit. The high-level ATPG prototype used in our work is mainly composed by constraint-driven test generation engine and fault simulation engine. Experimental result showed that more reduced/compact test set can be generated from the high-level ATPG.