Enhancing SAT-Based Test Pattern Generation

This paper presents modeling tools based on Boolean satisfiability (SAT) to solve problems of test generation for combinational circuits. It exploits an added layer to maintain circuit-related information and value justification relations to a generic SAT algorithm. It dovetails binary decision graphs (BDD) and SAT techniques to improve the efficiency of automatic test pattern generation (ATPG). More specifically, it first exploits inexpensive reconvergent fanout analysis of circuit to gather information on the local signal correlation by using BDD learning, then uses the above learned information to restrict and focus the overall search space of SAT-based ATPG. Its learning technique is effective and lightweight. The experimental results demonstrate the effectiveness of the approach.

Efficient Static Compaction of Test Patterns Using Partial Maximum Satisfiability

Static compaction methods aim at finding unnecessary test patterns to reduce the size of the test set as a post-process of test generation.Techniques based on partial maximum satisfiability are often used to track many hard problems in various domains,including artificial intelligence,computational biology,data mining,and machine learning.We observe that part of the test patterns generated by the commercial Automatic Test Pattern Generation(ATPG)tool is redundant,and the relationship between test patterns and faults,as a significant information,can effectively induce the test patterns reduction process.Considering a test pattern can detect one or more faults,we map the problem of static test compaction to a partial maximum satisfiability problem.Experiments on ISCAS89,ISCAS85,and ITC99 benchmarks show that this approach can reduce the initial test set size generated by TetraMAX18 while maintaining fault coverage.

HTDet:A Clustering Method Using Information Entropy for Hardware Trojan Detection

Hardware Trojans(HTs)have drawn increasing attention in both academia and industry because of their significant potential threat.In this paper,we propose HTDet,a novel HT detection method using information entropybased clustering.To maintain high concealment,HTs are usually inserted in the regions with low controllability and low observability,which will result in that Trojan logics have extremely low transitions during the simulation.This implies that the regions with the low transitions will provide much more abundant and more important information for HT detection.The HTDet applies information theory technology and a density-based clustering algorithm called Density-Based Spatial Clustering of Applications with Noise(DBSCAN)to detect all suspicious Trojan logics in the circuit under detection.The DBSCAN is an unsupervised learning algorithm,that can improve the applicability of HTDet.In addition,we develop a heuristic test pattern generation method using mutual information to increase the transitions of suspicious Trojan logics.Experiments on circuit benchmarks demonstrate the effectiveness of HTDet.

Simulation of ATPG Neural Network and Its Experimental Results

This paper first establishes a neural network model for logic circuits fromthe truth table by using linear equations theory, presents a kind of ATPG neuralnetwork model, and investigates energy local minima for the network- And then,it proposes the corresponding techniques to reduce the number of energy localminima as well as some approaches to escaping from local minimum of eliergyFinally, two simulation systems, the binary ATPG neural network and thecontinuous ATPG neural network, are implemented oli SUN 3/260 workstationin C language. The experimental results and their analysis and discussion aregiven. The preliminary experimental results show that this method is feasibleand promising.