ADVANCED FREQUENCY-DIRECTED RUN-LENTH BASED CODING SCHEME ON TEST DATA COMPRESSION FOR SYSTEM-ON-CHIP

Test data compression and test resource partitioning （TRP） are essential to reduce the amount of test data in system-on-chip testing. A novel variable-to-variable-length compression codes is designed as advanced fre- quency-directed run-length （AFDR） codes. Different [rom frequency-directed run-length （FDR） codes, AFDR encodes both 0- and 1-runs and uses the same codes to the equal length runs. It also modifies the codes for 00 and 11 to improve the compression performance. Experimental results for ISCAS 89 benchmark circuits show that AFDR codes achieve higher compression ratio than FDR and other compression codes.

Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction

This paper presents a test resource partitioning technique based on anefficient response compaction design called quotient compactor(q-Compactor). Because q-Compactor isa single-output compactor, high compaction ratios can be obtained even for chips with a small numberof outputs. Some theorems for the design of q-Compactor are presented to achieve full diagnosticability, minimize error cancellation and handle unknown bits in the outputs of the circuit undertest (CUT). The q-Compactor can also be moved to the load-board, so as to compact the outputresponse of the CUT even during functional testing. Therefore, the number of tester channelsrequired to test the chip is significantly reduced. The experimental results on the ISCAS ''89benchmark circuits and an MPEG 2 decoder SoC show that the proposed compaction scheme is veryefficient.

SOC可测试性设计与测试技术

超深亚微米工艺和基于芯核的设计给芯片系统(system-on-a-chip,SOC)测试带来了新的问题.对SOC可测试性设计与测试技术的国际研究现状及进展进行了广泛而深入的综述.从芯核级综述了数字逻辑、模拟电路、存储器、处理器4类芯核的可测试性设计与测试技术,从系统级综述了测试激励、测试响应和测试访问机制等SOC测试资源的设计以及压缩／解压缩与测试调度等测试资源划分、优化技术,并介绍了2个标准化组织开展的SOC测试标准工作.最后,展望了SOC测试未来的发展方向.

划分测试中测试用例最优分配问题研究

研究了划分测试中每个子域错误率已知,测试资源受约束时,测试用例如何合理分配的优化问题.主要考虑了两类测试用例分配问题:测试资源受约束的测试用例分配及测试资源受约束且各个子域的可靠性要达到一定要求时测试用例的分配,证明了带约束的测试用例最优分配问题是一个NPC问题.给出了动态规划求解方法,从理论上证明了该方法是最优的,并通过随机模拟将该方法与其它常见的测试用例分配策略进行分析比较,用实验数据验证了该方法能合理利用有限测试资源,有效地提高缺陷检测能力.

改进型FDR码对SoC测试数据的压缩及解压缩

针对SoC测试中的关键问题——测试数据的压缩,提出了一种改进型的FDR码编码方法,称为IFDR码。它将测试序列看做连续的0串和1串,从而用同一种编码方法同时对0游程和1游程进行编码,突破了FDR码仅能对0游程进行编码的限制。通过分析可知IFDR码的解压电路的结构较简单,所需要的额外硬件开销很小;对ISCAS 89标准电路的实验结果表明,与FDR码以及同类型的其他编码方法相比,该编码方法能获得更高的压缩率,从而可以更好地节省测试数据的存储空间和测试应用时间。

基于游程编码的测试数据压缩方法分析

基于游程编码的测试数据压缩方案能够有效地压缩测试数据。文中介绍了4种经典的游程编码方案,并对它们的压缩率进行了比较。

一种基于测试集分组的广义交替码

测试数据编码压缩是一类重要、经典的测试源划分(TRP)方法。本文提出了一种广义交替码,将FDR码、交替码都看作它的特例;又扩展了两步压缩方法,将原测试集划分成多组,每组采用不同的比值进行交替编码,综合了交替码与两步编码各自的优势,弥补了FDR码、交替码对某些电路测试集压缩的缺陷,得到了较好的压缩率。实验结果表明,与同类型的编码压缩方法相比,该方案具有更高的测试数据压缩率和较好的综合测试性能。