With the development of VLSI technology, testing design method has been one indispensable fact of the research of VLSI design methodology. Technology of testing design can observably reduce the cost of the chip and he...With the development of VLSI technology, testing design method has been one indispensable fact of the research of VLSI design methodology. Technology of testing design can observably reduce the cost of the chip and help win in time- to-market. Conventional methods of design for test improve the testing performance of the system by modifing the gate-level architecture generally. Re-search in high-level test synthesis has been emphasized on fitting for the trend of high-level VLSI design. In this paper, based on the analysis of different types of testing design methods, a novel compound strategy of design for test in VLSI system is proposed.展开更多
This paper describes a built-in self-test (BIST) hardware overheadminimization technique used during a BIST synthesis process. The technique inserts a minimal amountof BIST resources into a digital system to make it f...This paper describes a built-in self-test (BIST) hardware overheadminimization technique used during a BIST synthesis process. The technique inserts a minimal amountof BIST resources into a digital system to make it fully testable. The BIST resource insertion isguided by the results of symbolic testability analysis. It takes into consideration both BISTregister cost and wiring overhead in order to obtain the minimal area designs. A Simulated Annealingalgorithm is used to solve the overhead minimization problem. Experiments show that consideringwiring area during BIST synthesis results in smaller final designs as compared to the cases when thewiring impact is ignored.展开更多
文摘With the development of VLSI technology, testing design method has been one indispensable fact of the research of VLSI design methodology. Technology of testing design can observably reduce the cost of the chip and help win in time- to-market. Conventional methods of design for test improve the testing performance of the system by modifing the gate-level architecture generally. Re-search in high-level test synthesis has been emphasized on fitting for the trend of high-level VLSI design. In this paper, based on the analysis of different types of testing design methods, a novel compound strategy of design for test in VLSI system is proposed.
文摘This paper describes a built-in self-test (BIST) hardware overheadminimization technique used during a BIST synthesis process. The technique inserts a minimal amountof BIST resources into a digital system to make it fully testable. The BIST resource insertion isguided by the results of symbolic testability analysis. It takes into consideration both BISTregister cost and wiring overhead in order to obtain the minimal area designs. A Simulated Annealingalgorithm is used to solve the overhead minimization problem. Experiments show that consideringwiring area during BIST synthesis results in smaller final designs as compared to the cases when thewiring impact is ignored.
