Adding Pseudo-Random Test Sequence Generator in the Test Simulator for DFT Approach

This paper presents modified version of a realistic test tool suitable to Design For Testability （DFT） and Built-ln Self Test （BIST） environments. A comprehensive tool is developed in the form of a test simulator. The simulator is capable of providing a required goal of test for the Circuit Under Test （CUT）. The simulator uses the approach of fault diagnostics with fault grading procedures to provide the optimum tests. The current version of the simulator embeds features of exhaustive and pseudo-random test generation schemes along with the search solutions of cost effective test goals. The simulator provides facilities of realizing all possible pseudo-random sequence generators with all possible combinations of seeds. The tool is developed on a common Personal Computer （PC） platform and hence no special software is required. Thereby, it is a low cost tool hence economical. The tool is very much suitable for determining realistic test sequences for a targeted goal of testing for any CUT. The developed tool incorporates flexible Graphical User Interface （GUI） procedures and can be operated without any special programming skill. The tool is debugged and tested with the results of many bench mark circuits. Further, this developed tool can be utilized for educational purposes for many courses such as fault-tolerant computing, fault diagnosis, digital electronics, and safe-reliable-testable digital logic designs.

Efficient Activation Method of Hardware Trojan Based on Greedy Algorithm

To generate test vector sets that can efficiently activate hardware Trojans and improve probability of the hardware Trojan activation,an efficient hardware Trojan activation method is proposed based on greedy algorithm for combinatorial hardware Trojans. Based on the greedy algorithm and the recursive construction method in the combination test,the method formulates appropriate and useful greedy strategy and generates test vector sets with different combinatorial correlation coefficients to activate hardware Trojans in target circuits. The experiment was carried out based on advanced encryption standard（ AES） hardware encryption circuit,different combinatorial hardware Trojans were implanted in AES as target circuits,the experiment of detecting hardware Trojans in target circuits was performed by applying the proposed method and different combinatorial hardware Trojans in target circuits were activated successfully many times in the experiment. The experimental results showthat the test vector sets generated using the proposed method could effectively activate combinatorial hardware Trojans,improve the probability of the hardware Trojan being activated,and also be applied to practice.

Inflatable Wing Design Parameter Optimization Using Orthogonal Testing and Support Vector Machines

The robust parameter design method is a traditional approach to robust experimental design that seeks to obtain the optimal combination of factors/levels. To overcome some of the defects of the inflatable wing parameter design method, this paper proposes an optimization design scheme based on orthogonal testing and support vector machines （SVMs）. Orthogonal testing design is used to estimate the appropriate initial value and variation domain of each variable to decrease the number of iterations and improve the identification accuracy and efficiency. Orthogonal tests consisting of three factors and three levels are designed to analyze the parameters of pressure, uniform applied load and the number of chambers that affect the bending response of inflatable wings. An SVM intelligent model is established and limited orthogonal test swatches are studied. Thus, the precise relationships between each parameter and product quality features, as well the signal-to-noise ratio （SNR）, can be obtained. This can guide general technological design optimization.

High-dimensional Tests for Mean Vector: Approaches without Estimating the Mean Vector Directly

Several tests for multivariate mean vector have been proposed in the recent literature.Generally,these tests are directly concerned with the mean vector of a high-dimensional distribution.The paper presents two new test procedures for testing mean vector in large dimension and small samples.We do not focus on the mean vector directly,which is a different framework from the existing choices.The first test procedure is based on the asymptotic distribution of the test statistic,where the dimension increases with the sample size.The second test procedure is based on the permutation distribution of the test statistic,where the sample size is fixed and the dimension grows to infinity.Simulations are carried out to examine the finite-sample performance of the tests and to compare them with some popular nonparametric tests available in the literature.

Sign-based Test for Mean Vector in High-dimensional and Sparse Settings

In this article, we introduce a robust sparse test statistic which is based on the maximum type statistic. Both the limiting null distribution of the test statistic and the power of the test are analysed. It is shown that the test is particularly powerful against sparse alternatives. Numerical studies are carried out to examine the numerical performance of the test and to compare it with other tests available in the literature. The numerical results show that the test proposed significantly outperforms those tests in a range of settings, especially for sparse alternatives.