In-situ constructed SnO_(2) gradient buffer layer as a tight and robust interphase toward Li metal anodes in LATP solid state batteries

Li_(1.3)Al_(0.3)Ti_(1.7)(PO_(4))_(3)(LATP),of much interest owing to its high ionic conductivity,superior air stability,and low cost,has been regarded as one of the most promising solid-state electrolytes for next-generation solid-state lithium batteries(SSLBs).Unfortunately,the commercialization of SSLBs is still impeded by severe interfacial issues,such as high interfacial impedance and poor chemical stability.Herein,we proposed a simple and convenient in-situ approach to constructing a tight and robust interface between the Li anode and LATP electrolyte via a SnO_(2)gradient buffer layer.It is firmly attached to the surface of LATP pellets due to the volume expansion of SnO_(2)when in-situ reacting with Li metal,and thus effectively alleviates the physical contact loosening during cycling,as confirmed by the mitigated impedance rising.Meanwhile,the as-formed SnO_(2)/Sn/LixSn gradient buffer layer with low electronic conductivity successfully protects the LATP electrolyte surface from erosion by the Li metal anode.Additionally,the LixSn alloy formed at the Li surface can effectively regulate uniform lithium deposition and suppress Li dendrite growth.Therefore,this work paves a new way to simultaneously address the chemical instability and poor physical contact of LATP with Li metal in developing low-cost and highly stable SSLBs.

Solid electrolyte-electrode interface based on buffer therapy in solid-state lithium batteries

In the past few years,the all-solid lithium battery has attracted worldwide attentions,the ionic conductivity of some all-solid lithium-ion batteries has reached 10^(-3)-10^(-2) S/cm,indicating that the transport of lithium ions in solid electrolytes is no longer a major problem.However,some interface issues become research hotspots.Examples of these interfacial issues include the electrochemical decomposition reaction at the electrode-electrolyte interface;the low effective contact area between the solid electrolyte and the electrode etc.In order to solve the issues,researchers have pursued many different approaches.The addition of a buffer layer between the electrode and the solid electrolyte has been at the center of this endeavor.In this review paper,we provide a systematic summarization of the problems on the electrode-solid electrolyte interface and detailed reflection on the latest works of buffer-based therapies,and the review will end with a personal perspective on the improvement of buffer-based therapies.

Improved performance of polymer solar cells by using inorganic, organic, and doped cathode buffer layers

The interface between the active layer and the electrode is one of the most critical factors that could affect the device performance of polymer solar cells. In this work, based on the typical poly（3-hexylthiophene）：[6,6]-phenyl C61-butyric acid methyl ester （P3HT：PCBM） polymer solar cell, we studied the effect of the cathode buffer layer （CBL） between the top metal electrode and the active layer on the device performance. Several inorganic and organic materials commonly used as the electron injection layer in an organic light-emitting diode （OLED） were employed as the CBL in the P3HT：PCBM polymer solar cells. Our results demonstrate that the inorganic and organic materials like Cs2CO3, bathophenanthroline （Bphen）, and 8-hydroxyquinolatolithium （Liq） can be used as CBL to efficiently improve the device performance of the P3HT：PCBM polymer solar cells. The P3HT：PCBM devices employed various CBLs possess power conversion efficiencies （PCEs） of 3.0%-3.3%, which are ca. 50% improved compared to that of the device without CBL. Furthermore, by using the doped organic materials Bphen：Cs2CO3 and Bphen：Liq as the CBL, the PCE of the P3HT：PCBM device will be further improved to 3.5%, which is ca. 70% higher than that of the device without a CBL and ca. 10% increased compared with that of the devices with a neat inorganic or organic CBL.

High-power SiC MESFET using a dual p-buffer layer for an S-band power amplifier

A silicon carbide （SIC） based metal semiconductor field effect transistor （MESFET） is fabricated by using a standard SiC MESFET structure with the application of a dual p-buffer layer and a multi-recessed gate to the process for an S-band power amplifier. The lower doped upper-buffer layer serves to maintain the channel current, while the higher doped lowerbuffer layer is used to provide excellent electron confinement in the channel layer. A 20-mm gate periphery SiC MESFET biased at a drain voltage of 85 V demonstrates a pulsed wave saturated output power of 94 W, a linear gain of 11.7 dB, and a maximum power added efficiency of 24.3% at 3.4 GHz. These results are improved compared with those of the conventional single p-buffer MESFET fabricated in this work using the same process. A radio-frequency power output greater than 4.7 W/mm is achieved, showing the potential as a high-voltage operation device for high-power solid-state amplifier applications.

Preparation and Interface Studies on HgCdTe/CdTe/GaAs Grown by MOCVD

When we use MOCVD technique,an excellent CdTe epi-layer was grown on GaAs substrates and the CdTe/GaAs hybrid substrates suitable for growing Hg_(1-x)Cd_xTe(CMT)were obtained.The x value in CMT is between 0.2 and 0.8.The electrical properties of CMT depend upon the thickness of CdTe epi-layers.The CdTe/GaAs interface was examined by both scanning electron microscope(SEM)and electron auger spectra (EAS).The influence of defects observed at interface on electrical and optical properties of CMT fihns was dis- cussed.

Improved performance of microcrystalline silicon solar cell with graded-band-gap silicon oxide buffer layer

Microcrystalline silicon（μc-Si：H） solar cell with graded band gap microcrystalline silicon oxide（μc-SiOx：H） buffer layer is prepared by plasma enhanced chemical vapor deposition and exhibits improved performance compared with the cell without it. The buffer layer moderates the band gap mismatch by reducing the barrier of the p/i interface, which promotes the nucleation of the i-layer and effectively eliminates the incubation layer, and then enhances the collection efficiency of the cell in the short wavelength region of the spectrum. The p/i interface defect density also decreases from 2.2 × 10^12cm^-2to 5.0 × 10^11cm^-2. This graded buffer layer allows to simplify the deposition process for the μc-Si：H solar cell application.

金刚石表面化学镀Ni-P的研究

对金刚石表面化学镀Ni—P工艺进行了研究,用X射线衍射仪进行了物相鉴定,结果表明:高P化学Ni—P镀层为非晶态,热处理后镀层转变为Ni_3P晶态结构。同时证明:Ni—P镀层与金刚石没有发生界面反应。扫描电镜分析表明:Ni-P镀层与金刚石之间的结合状态良好。研究对镀液成分控制和施镀工艺进行了分析。

SiC_P/ZL109复合材料中SiC的界面行为

以常规 TEM为工具 ,研究了 Si CP/ ZL10 9复合材料中数十个 Si C颗粒及其界面 ,Si优先在 Si C表面上形核、长大 ,形成界面 Si,并形成大量 Si C/ Si界面。靠近 Si C界面的 Al基体中 ,普遍存在一层厚度小于 1μm的“亚晶铝带”,其内有大量位错。Si C与 Al、Si C与 Si之间虽然没有固定的晶体学位向关系 ,但是存在下列优先关系 :(110 3) Si C/ /(111) Al,[112 0 ]Si C/ / [110 ]Al;(110 1) Si C/ / (111) Si;[112 0 ]Si C/ / [112

ZnO薄膜p型转变的难点及解决新方法

论述了ZnO薄膜p型转变的难点及其解决方法的最新研究进展,并讨论了Al+N+H共掺杂生长p-ZnO膜的掺杂机制,提出多层缓冲层生长工艺以实现p-ZnO薄膜的可控掺杂,进而优化薄膜性能。

平面P波入射下深埋圆形复合式衬砌隧道抗减震机理研究

基于Fourier-Bessel级数展开法,研究深埋圆形三层复合式衬砌洞室在平面P波入射下的动应力集中问题,并给出三层衬砌洞室动应力集中系数级数解析解;依托某IX度地震区管道隧道实际工程,分析不同衬砌刚度组合和厚度组合对洞室动应力集中系数的影响。研究表明:注浆加固洞室围岩和设置减震层都可以降低二次衬砌动应力集中系数;增大围岩注浆区弹性模量和厚度,有利于减小衬砌动应力集中系数,最优围岩注浆区厚度为1倍洞室净空半径;减震层弹性模量降低,减震层厚度增大,二次衬砌动应力集中系数变小,减震层弹性模量宜低于围岩弹模1/20,最优减震层厚度宜取1/50的洞室内净空半径。最后针对实际管道隧道抗减震技术,考虑围岩稳定性,提出"围岩-加固圈-减震层-衬砌"新型减震结构,分析结果表明:对比其他三种抗减震措施,新型减震结构的减震效果最好。

SiC_p/Al-Si复合材料中SiC/Al界面处亚晶铝带的研究

通过利用 TEM研究 Si Cp/ Al- Si复合材料发现 :Si C/ Al界面结合紧密 ,在靠近 Si C界面的 Al基体中 ,有一层厚度小于 1μm的“亚晶铝带”,它紧靠 Si C表面形成 ,与远离 Si C的 Al基体有几度的位向差 ;这种“亚晶铝带”在 Si C/ Al界面上普遍存在 ,其内有大量位错。

p/i界面掺碳缓冲层沉积时间对非晶硅太阳电池性能的影响

本文研究了pin型非晶硅(a-Si)太阳电池p/i界面掺碳缓冲层(C-buffer layer)沉积时间对电池效率和稳定性的影响。研究发现,随着掺碳缓冲层沉积时间的增加,太阳电池的初始效率有所增加,当沉积时间增加到约60s时,电池的初始效率达最大值,而后随着沉积时间的继续增加,电池效率下降。而在太阳电池的稳定性方面,当缓冲层沉积时间小于50s时,随着沉积时间的增加,电池衰退率增大;大于50s后,电池的衰退率又随沉积时间的增大而减小。

界面缓冲层对全旋涂式PVDF–TrFE/ZnO量子点传感器压电性能的影响

首先制备了聚偏氟乙烯–三氟乙烯(PVDF-TrFE)/氧化锌(ZnO)量子点复合压电薄膜,采用广角X射线衍射仪、激光共聚焦显微镜及原子力显微镜等对其结构及形貌进行了表征。以其作为核心功能层,以聚乙烯吡咯烷酮(PVP)为界面缓冲层,采用全旋涂法成功制备了PVDF–TrFE/ZnO量子点压电传感器,分别利用落球试验及激振试验研究了PVP对传感器压电性能的影响。结果表明,添加PVP界面缓冲层的压电传感器输出电压为(1.84±0.06) V,误差棒较小,且在抗疲劳测试中经过3?500次机械循环后,输出电压仍保持在0.83 V。一方面,PVP缓冲层的亲水性使其分别与压电层中的ZnO量子点、聚(3,4-乙撑二氧噻吩):聚苯乙烯磺酸(PEDOT:PSS)电极层紧密结合,利于电荷在压电层与电极之间的传输;另一方面,PVP缓冲层良好的成膜性改善了压电层和PEDOT:PSS电极层的层间接触,利于收集更多的压电层电荷。制备的全旋涂式PVDF–TrFE/ZnO量子点压电传感器在柔性可穿戴领域具有广阔的应用前景。

具有p-GaN岛状埋层耐压结构的横向AlGaN/GaN高电子迁移率晶体管

GaN基高电子迁移率晶体管(HEMT)相对较低的击穿电压严重限制了其大功率应用.为了进一步改善器件的击穿特性,通过在n-GaN外延缓冲层中引入六个等间距p-GaN岛掩埋缓冲层(PIBL)构成p-n结,提出一种基于p-GaN埋层结构的新型高耐压AlGaN/GaN HEMT器件结构.Sentaurus TCAD仿真结果表明,在关态高漏极电压状态下,p-GaN埋层引入的多个反向p-n结不仅能够有效调制PIBL AlGaN/GaN HEMT的表面电场和体电场分布,而且对于缓冲层泄漏电流有一定的抑制作用,这保证了栅漏间距为10μm的PIBL HEMT能够达到超过1700 V的高击穿电压(BV),是常规结构AlGaN/GaN HEMT击穿电压(580 V)的3倍.同时,PIBL结构AlGaN/GaN HEMT的特征导通电阻仅为1.47 m?·cm^2,因此获得了高达1966 MW·cm^(-2)的品质因数(FOM=BV^2/R_(on,sp)).相比于常规的AlGaN/GaN HEMT,基于新型p-GaN埋岛结构的HEMT器件在保持较低特征导通电阻的同时具有更高的击穿电压,这使得该结构在高功率电力电子器件领域具有很好的应用前景.

嵌入式TCP/IP协议LwIP的内存管理机制研究

该文研究了应用于嵌入式系统中的一种轻量级TCP/IP协议栈—LwIP(Light-weight IP)的内存管理机制,在此基础上提出了一种基于该内存管理机制的底层网络接口收发模块的实现方法,并在开发板上进行了仿真测试,为将该协议栈成功移植到开源的μC/OS-II嵌入式实时操作系统并最终实现基于LwIP协议栈的嵌入式Web服务器奠定了重要基础。

阴极界面修饰层改善平面p-i-n型钙钛矿太阳能电池的光伏性能

有机/无机杂化金属卤化物钙钛矿半导体材料结合了有机材料良好的溶液可加工性以及无机材料优越的光电特性,近几年受到了热捧,成为太阳能电池领域一颗耀眼的明星.伴随着钙钛矿薄膜结晶过程和形貌的优化、器件结构的改进以及电极界面材料的开发,这类有机/无机杂化金属卤化物钙钛矿太阳能电池的光电转换效率从最初的3.8%迅速提高到目前最高的22.1%.其中界面工程在提升器件性能上发挥着极其重要的作用.本文总结了平面p-i-n型钙钛矿太阳能电池中阴极界面修饰层(CBL)的研究进展.CBL从材料上讲可分为无机金属氧化物、金属或金属盐以及有机材料,从构成上讲可分为单层CBL、双层CBLs以及共混型CBL.本文对这些类型的CBL分别给予详细的介绍.最后,我们归纳出CBL在改善器件效率和稳定性上所起的作用以及理想CBL所应满足的要求,希望能为以后阴极界面修饰材料的设计提供一定的借鉴.

最佳缓冲层下微晶硅薄膜pin型太阳电池的数值模拟

运用由美国宾州大学开发的AMPS-1D计算机模拟软件,模拟了在最佳缓冲层和无缓冲层的情况下,太阳电池的各性能参数随本征层厚度的变化、太阳电池的J-V特性和量子效率以及不同晶化率的本征活性层对太阳电池各性能参数和量子效率的影响。模拟结果表明:在最佳缓冲层100nm时,太阳电池的各性能参数比无缓冲层时有所提高;随着本征层晶化率X_c的增大,太阳电池的量子效率QE在长波段有明显提高;本征层晶化率高的太阳电池,具有较高的短路电流J_(SC),低的开路电压V_(OC)、转换效率Eff和填充因子FF。

Optimization of n/i and i/p buffer layers in n-i-p hydrogenated microcrystalline silicon solar cells

Hydrogenated microcrystalline silicon （μc-Si：H） intrinsic films and solar cells with n-i-p configuration were prepared by plasma enhanced chemical vapor deposition （PECVD）. The influence of n/i and i/p buffer layers on the μc-Si：H cell performance was studied in detail. The experimental results demonstrated that the efficiency is much improved when there is a higher crystallinity at n/i interface and an optimized a-Si：H buffer layer at i/p interface. By combining the above methods, the performance of μc-Si：H single-junction and a-Si：H/μc-Si：H tandem solar cells has been significantly improved.

铁电场效应晶体管材料设计的研究进展

铁电场效应晶体管(FeFET)作为最有潜力的下一代非易失性存储器之一,引起研究人员的广泛关注。本文系统阐述了Fe FET的工作原理及结构设计,介绍了Fe FET结构中铁电材料和缓冲层材料的探索历程及所对应的器件性能。本文提出了一种新型Fe FET结构设计,有望改善薄膜之间的界面效应。最后总结了Fe FET的研究进展,并对未来研究做出展望。

Enhancement of the efficiency and stability of planar p-i-n perovskite solar cells via incorporation of an amine-modified fullerene derivative as a cathode buffer layer

A methanol-soluble diamine-modified fullerene derivative(denoted as PCBDANI)was applied as an efficient cathode buffer layer(CBL)in planar p-i-n perovskite solar cells(pero-SCs)based on the CH_3NH_3PbI_(3-x)Cl_x absorber.The device with PCBDANI single CBL exhibited significantly improved performance with a power conversion efficiency(PCE)of 15.45%,which is approximately17%higher than that of the control device without the CBL.The dramatic improvement in PCE can be attributed to the formation of an interfacial dipole at the PCBM/Al interface originating from the amine functional group and the suppression of interfacial recombinationby the PCBDANI interlayer.To further improve the PCE of pero-SCs,PCBDANI/LiF double CBLs were introduced between PCBM and the top Al electrode.An impressive PCE of 15.71%was achieved,which is somewhat higher than that of the devices with LiF or PCBDANI single CBL.Besides the PCE,the long-term stability of the device with PCBDANI/LiF double CBLs is also superior to that of the device with LiF single CBL.