Integration Mechanism of Ideological and Political Education with Specialized Knowledge in the Course of Green Building Design

This paper aims to explore the integration of ideological and political education with specialized knowledge in the course of green building design.Through an analysis of the green building design course,combined with the current social development background and the need for ecological and environmental protection,the study investigates how to effectively integrate ideological and political education elements into course instruction to enhance the comprehensive quality and green design capabilities of architecture students.The paper analyzes the content and characteristics of the green building design course and proposes an integration mechanism for ideological and political education in green building design teaching,aiming to cultivate architecture talents with green design concepts and good ideological and political qualities.

Matching processing in the design of integrated circuits

In the design of the integrated circuits, in order to ensure that the designed products conform to the presupposed parameters, while designing the schematic diagrams of the circuits, we should also strengthen the layout design. Especially in the design of the analog circuits, in the layout design, there is a high degree of matching requirement for the MOS. It will have an important impact on the performance of the chips. Based on this perspective, the author of this paper analyzes how to realize the matching of the three aspects of the MOS, the resistance and the capacitance in the integrated circuit design, in order to avoid the problem of the mismatch due to the arts and crafts.

Concise Modeling of Amorphous Dual-Gate In-Ga-Zn-O Thin-Film Transistors for Integrated Circuit Designs

An analytical model for current-voltage behavior of amorphous In-Ga-Zn-O thin-film transistors（a-IGZO TFTs）with dual-gate structures is developed.The unified expressions for synchronous and asynchronous operating modes are derived on the basis of channel charges,which are controlled by gate voltage.It is proven that the threshold voltage of asynchronous dual-gate IGZO TFTs is adjusted in proportion to the ratio of top insulating capacitance to the bottom insulating capacitance（C_（TI）/C_（BI））.Incorporating the proposed model with Verilog-A,a touch-sensing circuit using dual-gate structure is investigated by SPICE simulations.Comparison shows that the touch sensitivity is increased by the dual-gate IGZO TFT structure.

High performance integrated photonic circuit based on inverse design method

The basic indexes of all-optical integrated photonic circuits include high-density integration,ultrafast response and ultralow energy consumption.Traditional methods mainly adopt conventional micro/nano-structures.The overall size of the circuit is large,usually reaches hundreds of microns.Besides,it is difficult to balance the ultrafast response and ultra-low energy consumption problem,and the crosstalk between two traditional devices is difficult to overcome.Here,we propose and experimentally demonstrate an approach based on inverse design method to realize a high-density,ultrafast and ultra-low energy consumption integrated photonic circuit with two all-optical switches controlling the input states of an all-optical XOR logic gate.The feature size of the whole circuit is only 2.5μm×7μm,and that of a single device is 2μm×2μm.The distance between two adjacent devices is as small as 1.5μm,within wavelength magnitude scale.Theoretical response time of the circuit is 150 fs,and the threshold energy is within 10 fJ/bit.We have also considered the crosstalk problem.The circuit also realizes a function of identifying two-digit logic signal results.Our work provides a new idea for the design of ultrafast,ultra-low energy consumption all-optical devices and the implementation of high-density photonic integrated circuits.

Microwave Integrated Circuit Design Handbook

作者:Reinmut K.Hoffmann(1984 IEEE微波奖获得者) 出版:Artech House公司(美国)1987年本书给出适于微波工程师和研究人员应用的有关MIC方面的基础技术、电性能和设计。侧重于电性能分析和设计,强调应用。对于每一种设计技术和应用均作出较清楚的叙述和完整的处理。本书尽量给出电路的物理描述,避免过于冗长的数学公式,内容包含对下列议题的详细评述与研讨:

Design, Fabrication, and Modeling of CMOS-Compatible Double Photodiode

A double photodiode (PD) constructed by p+/N-well junction and N-well/p-sub junction was designed and fabricated in a UMC 0.18-μm CMOS process. Based on the device structure and mechanism of double PD, a novel small-signal equivalent circuit model considering the carrier transit effect and the parasitic RC time constant was presented. By this model with complete electronic components, the double PD can be incorporated in a commercial circuit simulator. The component values were extracted by fitting the measured S-parameters using simulated annealing algorithm, and a good agreement between the measurement and the simulation results was achieved. © 2017, Tianjin University and Springer-Verlag Berlin Heidelberg.

Design and Evaluation of SIMpliLife, an NFC Platform to Ease Day-to-Day Actions of People＇s Life

In this paper the authors describe the design, prototyping and evaluation of SIMpliLife, a framework for mobile phones with the aim of making people＇s life easier, providing day-to-day services such as payment, ticketing and information retrieval by means of NFC （Near Field Communication） technology. It was developed via the collaboration between two research labs of Sapienza University of Rome： the RFID （Radio Frequency Identification） Lab and the Usability and Accessibility Lab （LUA）, both belonging to CATTID （Centre for Applications of Teleservices and of Technologies for Innovation in Digital world） research centre. Technically, SIMpliLife is a SIM-based platform for NFC mobile phones that interfaces several applications able to manage the abovementioned services. The high-level User Interface has been developed by means of Smart Card Web Server （SCWS） technology, thus providing enhanced user experience if compared to traditional SIM-based implementations based on SIM Toolkit.

Design and Implementation of an Efficient Reversible Comparator Using TR Gate

Reversible logic is a new emerging technology with many promising applications in optical information processing, low power (Complementary Metal Oxide Semiconductor) CMOS design, (De Oxy RiboNucleic Acid) DNA computing, etc. In industrial automation, comparators play an important role in segregating faulty patterns from good ones. In previous works, these comparators have been implemented with more number of reversible gates and computational complexity. All these comparators use propagation technique to compare the data. This will reduce the efficiency of the comparators. To overcome the problem, this paper proposes an efficient comparator using (Thapliyal Ranganathan) TR gate utilizing full subtraction and half subtraction algorithm which will improve the computation efficiency. The comparator design using half subtraction algorithm shows an improvement in terms of quantum cost. The comparator design using full subtraction algorithm shows effectiveness in reducing number of reversible gates required and garbage output.

Challenges to Data-Path Physical Design Inside SOC

Previously,a single data-path stack was adequate for data-path chips,and the complexity and size of the data-path was comparatively small.As current data-path chips,such as system-on-a-chip (SOC),become more complex,multiple data-path stacks are required to implement the entire data-path.As more data-path stacks are integrated into SOC,data-path is becoming a critical part of the whole giga-scale integrated circuits (GSI) design.The traditional physical design methodology can not satisfy the data-path performance requirements,because it can not accommodate the data-path bit-sliced structure and the strict performance (such as timing,coupling,and crosstalk) constraints.Challenges in the data-path physical design are addressed.The fundamental problems and key technologies in data-path physical design are analysed.The corresponding researches and solutions in this research field are also discussed.

基于ADS软件的串联谐振电路实验优化设计

虚拟仿真软件是进行高校工科实验课程的必备工具,针对研究性强、涉及实验设备及元器件较多的复杂实验,虚拟仿真软件对实验设计有很好的支撑作用。该文针对电工电子基础实验中的串联谐振电路实验,开展了基于ADS电磁仿真软件的射频串联谐振电路实验的优化设计,通过提出基于ADS软件的电路优化设计方法,可以有效验证RLC串联谐振的品质因素、谐振频率与谐振带宽的计算公式,并实现射频串联谐振电路的参数扫描及优化设计。该虚拟仿真方法的提出,有助于更直观、更便捷地讲授RLC串联谐振电路的工作原理和实验流程,提高电路优化设计效果。

基于设计思维的STEM教育创新课程研究及启示*——以斯坦福大学d.loft STEM课程为例

随着全球经济与科学技术的快速发展,STEM教育已成为世界各国科技创新人才培养和教育教学改革的重要战略和途径。探索STEM教育应用模式,开发跨学科融合的STEM课程,是推动STEM教育开展的关键。为促进我国STEM教育课程设计与开发,该研究以美国斯坦福大学教育学院与设计学院合作的d.loft STEM Learning项目中的STEM课程为例进行案例研究,在详细介绍课程整体结构、课程活动设计及实施的基础上,分析并总结归纳该课程的特点。主要包括:基于设计思维培养学生核心技能与STEM素养,课程活动目标与美国《下一代科学教育标准》相对应,以真实问题与项目为载体实现跨学科整合,提供丰富的学习支架与工具促进有效学习的发生。在此基础上,围绕STEM教育与设计思维的核心理念,从学生能力培养出发,构建了基于设计思维的跨学科STEM课程模型,并提出相关实施建议,为STEM教育实践提供有价值的借鉴。

Compact 16-channel integrated charge-sensitive preamplifier module for silicon strip detectors

In this study,a compact 16-channel integrated charge-sensitive preamplifier named the smart preamplifier(SPA)was developed to support the large-scale detector array used in modern nuclear physics experiments.Two types of SPA,namely SPA02 and SPA03(with external field effect transistor),have been manufactured to match silicon detectors with small and large capacitances,respectively.The characteristics of the SPA include fast response of typically less than 6 ns for pulse rising time and low equivalent noise of 1.5 keV at zero input capacitance.The energy sensitivity and pulse decay time can be easily adjusted by changing the feedback capacitance Cfand resistance Rfin various applications.A good energy resolution of 24.4 keV for 5.803-MeV alpha particles from 244 Cm was achieved using a small-sized Si-PIN detector;for the silicon strip detectors in the test with the alpha source,a typical energy resolution of 0.6–0.8%was achieved.The integrated SPA has been employed in several experiments of silicon strip detectors with hundreds of channels,and a good performance has been realized.

Trending IC design directions in 2022

For the non-stop demands for a better and smarter society, the number of electronic devices keeps increasing exponentially;and the computation power, communication data rate, smart sensing capability and intelligence are always not enough. Hardware supports software, while the integrated circuit(IC) is the core of hardware. In this long review paper, we summarize and discuss recent trending IC design directions and challenges, and try to give the readers big/cool pictures on each selected small/hot topics. We divide the trends into the following six categories, namely, 1) machine learning and artificial intelligence(AI) chips, 2) communication ICs, 3) data converters, 4) power converters, 5) imagers and range sensors, 6) emerging directions. Hope you find this paper useful for your future research and works.

Challenges and opportunities toward fully automated analog layout design

Realizing the layouts of analog/mixed-signal(AMS)integrated circuits(ICs)is a complicated task due to the high design flexibility and sensitive circuit performance.Compared with the advancements of digital IC layout automation,analog IC layout design is still heavily manual,which leads to a more time-consuming and error-prone process.In recent years,significant progress has been made in automated analog layout design with emerging of several open-source frameworks.This paper firstly reviews the existing state-of-the art AMS layout synthesis frameworks with focus on the different approaches and their individual challenges.We then present recent research trends and opportunities in the field.Finally,we summaries the paper with open questions and future directions for fully-automating the analog IC layout.

Three-dimensional global interconnect based on a design window

Based on a stochastic wire length distributed model, the interconnect distribution of a three-dimensional integrated circuit （3D IC） is predicted exactly. Using the results of this model, a global interconnect design window for a giga-scale system-on-chip （SOC） is established by evaluating the constraints of 1） wiring resource, 2） wiring bandwidth, and 3） wiring noise. In comparison to a two-dimensional integrated circuit （2D IC） in a 130-nm and 45-nm technology node, the design window expands for a 3D IC to improve the design reliability and system performance, further supporting 3D IC application in future integrated circuit design.

TEST OF BOARD-LEVEL BOUNDARY SCAN INTEGRITY

The IEEE Standard 1149.1 boundary scan (BS) implementation provides the internal access required for testing the digital printed circuit board (PCB). However, the integrity of the boundary scan test infrastructure should be tested first to guarantee the validation of the results of the rest functional test and diagnosis. This paper describes the fault models and test principles of the BS test access port (TAP) lines on PCBs. A test algorithm with high fault coverage and short time is then presented for the PCB on which all ICs are BS ones.

模拟集成电路设计课程实验项目驱动式教学改革

基于高校模拟集成电路设计课程实验项目分散且教学目标不明确,缺乏系统性和工程应用性,提出了项目驱动式教学改革。以与企业合作的工程项目为基础设立实验项目,并分解成由易及难的多个实验题目,分阶段、分步骤完成实验内容,最终完成模拟集成电路设计全流程实验,以“带隙基准电压源芯片全定制设计实验”为例阐述了实施步骤。课程实验项目采用驱动式教学加深了学生对课程内容的理解,有助于培养学生扎实的工程实践能力。

“教赛”一体“射频集成电路”研究生课程实践

针对新时代背景下研究生教育问题,以面向电子信息类相关研究生课程为对象,引入电子竞赛内容作为教学设计及工程实践,以赛促课,探索满足研究生创新能力培养模式要求的“教赛”一体研究生专业课程建设方法。以江苏大学电气信息工程学院开设的“射频集成电路”课程为例,将“研创赛”相关内容有机高效地融入课堂,在掌握理论知识的同时,有效提升研究生自主学习能力和创新实践能力。

“艺科融合”背景下人工智能融入艺术设计的混合式教学

对人工智能融入艺术设计教学的课程建设进行了分析和梳理。以目前设计类人才跨学科培养存在的问题为出发点,遵循“学科融合、专业交叉、技术支持、资源共享”的思想,在师资、技术、资源、课程、平台各个维度上进行跨界融合。打破了学科的界限,组建教师团队和虚拟教研室;参考多所院校的课程体系,对教学资源进行了融合和优化;教学案例中融入行业情境,强化学生的行业能力;以学生为中心,应用为导向,建立共享平台并开展混合式教学。通过构建跨学科的复合课程资源,探索开放式课程教学模式和数字人文教学方法,建立教学质量评价体系,使整个教学环节形成了闭环,使原本割裂的两个学科版块间形成互动发展的良性态势。课程形成了“艺科融合”设计人才培养模式,体现了“新文科”思维的建设思想,为同类课程的建设提供了借鉴和参考。

“岗课赛证”融通视域下物联网系统设计课程教学改革探索

针对现阶段高职院校物联网专业实施“岗课赛证”融通教学过程中存在职业岗位普适性较低、课程项目化程度不高、技能大赛融合不紧密、职业证书缺乏选择性等问题,分析岗课赛证四要素融通的基本逻辑,提出以课程为核心,以岗位为依据,以竞赛为载体,以证书为评价标准的教学改革思路。以物联网系统设计课程中的模块1为例,在教学设计、教学实施、教学效果三个方面,开展“岗课赛证”融通的教学改革实践。