配电线路长期暴露于自然环境下,易受强对流天气影响而发生故障。2022年4月19日午后,受大风、雷电等高影响天气影响,陇南市13条配电线路先后出现故障。利用陇南市自动气象观测站的极大风速和闪电定位数据以及风云4A(FY-4A)红外云图、探...配电线路长期暴露于自然环境下,易受强对流天气影响而发生故障。2022年4月19日午后,受大风、雷电等高影响天气影响,陇南市13条配电线路先后出现故障。利用陇南市自动气象观测站的极大风速和闪电定位数据以及风云4A(FY-4A)红外云图、探空资料、多普勒天气雷达等资料,对此次强对流天气过程及其对电网影响进行分析。结果表明:(1)此次强对流天气以雷电、雷暴大风天气为主,西和、礼县、武都、康县等县(区)出现大面积用户停电和电力负荷损失等不利影响。(2)强对流发展主要受高原槽和切变线共同影响,在“上冷下暖”的大气层结不稳定条件下,由地面辐合线触发较强的雷暴大风天气;卫星云图和雷达回波也显示对流云团的发生发展与地面雷暴大风相吻合。(3)陇南市配电线路故障范围分布与强对流天气发生时间和过境路径基本一致,利用逐10 min极大风速和闪电定位数据,探讨得出当极大风速值超过15.0 m·s^(-1)、或正地闪电流强度超过43 k A、或负地闪电流强度超过26 k A时,配电线路发生故障的可能性较大。展开更多
Under different conditions, the highest detection probability should be acquired while receiving laser echo during laser pulse range finding. The threshold voltage of the signal detection can be set corresponding ...Under different conditions, the highest detection probability should be acquired while receiving laser echo during laser pulse range finding. The threshold voltage of the signal detection can be set corresponding to different conditions by using resistor network. As a feedback loop, automatic noise threshold circuit could change the threshold voltage following the noise level. The threshold can track the noise closely, rapidly and accurately by adopting this combination. Therefore, the receiving capability of laser echo receiving system will be maximized, and it can detect weaker laser pulse from noise.展开更多
As process technology development,model order reduction( MOR) has been regarded as a useful tool in analysis of on-chip interconnects. We propose a weighted self-adaptive threshold wavelet interpolation MOR method on ...As process technology development,model order reduction( MOR) has been regarded as a useful tool in analysis of on-chip interconnects. We propose a weighted self-adaptive threshold wavelet interpolation MOR method on account of Krylov subspace techniques. The interpolation points are selected by Haar wavelet using weighted self-adaptive threshold methods dynamically. Through the analyses of different types of circuits in very large scale integration( VLSI),the results show that the method proposed in this paper can be more accurate and efficient than Krylov subspace method of multi-shift expansion point using Haar wavelet that are no weighted self-adaptive threshold application in interest frequency range,and more accurate than Krylov subspace method of multi-shift expansion point based on the uniform interpolation point.展开更多
Digital circuits operating in the sub-threshold regime consume the least energy. The strict energy constraints are desired in the applications which work at the lowest possible supply voltage. On the other hand, the c...Digital circuits operating in the sub-threshold regime consume the least energy. The strict energy constraints are desired in the applications which work at the lowest possible supply voltage. On the other hand, the conventional design flow utilizes the technology library provided by the foundry with a fixed voltage boundary, which causes problems when the supply scales down to the sub-threshold regime. In this paper, we present a design methodology to characterize the existing cell library with Liberty NCX to facilitate the standard design flow. It is demonstrated in 0.13 μm complementary metal-oxide-semiconductor （CMOS） technology with the supply voltage of 300 mV.展开更多
This paper presents a novel approach to design robust Source Coupled Logic (SCL) for implementing ultra low power circuits. In this paper, we propose two different source coupled logic structures and analyze the perfo...This paper presents a novel approach to design robust Source Coupled Logic (SCL) for implementing ultra low power circuits. In this paper, we propose two different source coupled logic structures and analyze the performance of these structures with STSCL (Sub-threshold SCL). The first design under consideration is DTPMOS as load device which analyses the performance of Dynamic Threshold SCL (DTSCL) Logic with previous source coupled logic for ultra low power operation. DTSCL circuits exhibit a better power-delay Performance compared with the STSCL Logic. It can be seen that the proposed circuit provides 56% reduction in power delay product. The second design under consideration uses basic current mirror active load device to provide required voltage swing. Current mirror source coupled logic (CMSCL) can be used for high speed operation. The advantage of this design is that it provides 54% reduction in power delay product over conventional STSCL. The main drawback of this design is that it provides a higher power dissipation compared to other source coupled logic structures. The proposed circuit provides lower sensitivity to temperature and power supply variation, with a superior control over power dissipation. Measurements of test structures simulated in 0.18 μm CMOS technology shows that the proposed DTSCL logic concept can be utilized successfully for bias currents as low as 1 pA. Measurements show that existing standard cell libraries offer a good solution for ultra low power SCL circuits. Cadence Virtuoso schematic editor and Spectre Simulation tools have been used.展开更多
文摘配电线路长期暴露于自然环境下,易受强对流天气影响而发生故障。2022年4月19日午后,受大风、雷电等高影响天气影响,陇南市13条配电线路先后出现故障。利用陇南市自动气象观测站的极大风速和闪电定位数据以及风云4A(FY-4A)红外云图、探空资料、多普勒天气雷达等资料,对此次强对流天气过程及其对电网影响进行分析。结果表明:(1)此次强对流天气以雷电、雷暴大风天气为主,西和、礼县、武都、康县等县(区)出现大面积用户停电和电力负荷损失等不利影响。(2)强对流发展主要受高原槽和切变线共同影响,在“上冷下暖”的大气层结不稳定条件下,由地面辐合线触发较强的雷暴大风天气;卫星云图和雷达回波也显示对流云团的发生发展与地面雷暴大风相吻合。(3)陇南市配电线路故障范围分布与强对流天气发生时间和过境路径基本一致,利用逐10 min极大风速和闪电定位数据,探讨得出当极大风速值超过15.0 m·s^(-1)、或正地闪电流强度超过43 k A、或负地闪电流强度超过26 k A时,配电线路发生故障的可能性较大。
文摘Under different conditions, the highest detection probability should be acquired while receiving laser echo during laser pulse range finding. The threshold voltage of the signal detection can be set corresponding to different conditions by using resistor network. As a feedback loop, automatic noise threshold circuit could change the threshold voltage following the noise level. The threshold can track the noise closely, rapidly and accurately by adopting this combination. Therefore, the receiving capability of laser echo receiving system will be maximized, and it can detect weaker laser pulse from noise.
基金Sponsored by the Fundamental Research Funds for the Central Universities(Grant No.HIT.NSRIF.2016107)the China Postdoctoral Science Foundation(Grant No.2015M581447)
文摘As process technology development,model order reduction( MOR) has been regarded as a useful tool in analysis of on-chip interconnects. We propose a weighted self-adaptive threshold wavelet interpolation MOR method on account of Krylov subspace techniques. The interpolation points are selected by Haar wavelet using weighted self-adaptive threshold methods dynamically. Through the analyses of different types of circuits in very large scale integration( VLSI),the results show that the method proposed in this paper can be more accurate and efficient than Krylov subspace method of multi-shift expansion point using Haar wavelet that are no weighted self-adaptive threshold application in interest frequency range,and more accurate than Krylov subspace method of multi-shift expansion point based on the uniform interpolation point.
基金supported by the Important National S&T Special Project of China under Grant No.2011ZX01034-002-001-2
文摘Digital circuits operating in the sub-threshold regime consume the least energy. The strict energy constraints are desired in the applications which work at the lowest possible supply voltage. On the other hand, the conventional design flow utilizes the technology library provided by the foundry with a fixed voltage boundary, which causes problems when the supply scales down to the sub-threshold regime. In this paper, we present a design methodology to characterize the existing cell library with Liberty NCX to facilitate the standard design flow. It is demonstrated in 0.13 μm complementary metal-oxide-semiconductor （CMOS） technology with the supply voltage of 300 mV.
文摘This paper presents a novel approach to design robust Source Coupled Logic (SCL) for implementing ultra low power circuits. In this paper, we propose two different source coupled logic structures and analyze the performance of these structures with STSCL (Sub-threshold SCL). The first design under consideration is DTPMOS as load device which analyses the performance of Dynamic Threshold SCL (DTSCL) Logic with previous source coupled logic for ultra low power operation. DTSCL circuits exhibit a better power-delay Performance compared with the STSCL Logic. It can be seen that the proposed circuit provides 56% reduction in power delay product. The second design under consideration uses basic current mirror active load device to provide required voltage swing. Current mirror source coupled logic (CMSCL) can be used for high speed operation. The advantage of this design is that it provides 54% reduction in power delay product over conventional STSCL. The main drawback of this design is that it provides a higher power dissipation compared to other source coupled logic structures. The proposed circuit provides lower sensitivity to temperature and power supply variation, with a superior control over power dissipation. Measurements of test structures simulated in 0.18 μm CMOS technology shows that the proposed DTSCL logic concept can be utilized successfully for bias currents as low as 1 pA. Measurements show that existing standard cell libraries offer a good solution for ultra low power SCL circuits. Cadence Virtuoso schematic editor and Spectre Simulation tools have been used.
