Characteristics and threshold voltage model of GaN-based FinFET with recessed gate

In this work, AlGaN/GaN FinFETs with different fin widths have been successfully fabricated, and the recessed-gate FinFETs are fabricated for comparison. The recessed-gate FinFETs exhibit higher transconductance value and positive shift of threshold voltage. Moreover, with the fin width of the recessed-gate FinFETs increasing, the variations of both threshold voltage and the transconductance increase. Next, transfer characteristics of the recessed-gate FinFETs with different fin widths and recessed-gate depths are simulated by Silvaco software. The relationship between the threshold voltage and the AlGaN layer thickness has been investigated. The simulation results indicate that the slope of threshold voltage variation reduces with the fin width decreasing. Finally, a simplified threshold voltage model for recessed-gate FinFET is established,which agrees with both the experimental results and simulation results.

A threshold voltage analytical model for high-k gate dielectric MOSFETs with fully overlapped lightly doped drain structures

We investigate the influence of voltage drop across the lightly doped drain（LDD） region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson＇s equation in the silicon and gate dielectric layers.The model can predict the fringing-induced barrier lowering effect and the short channel effect.It is also valid for non-LDD MOSFETs.Based on this model,the relationship between threshold voltage roll-off and three parameters,channel length,drain voltage and gate dielectric permittivity,is investigated.Compared with the non-LDD MOSFET,the LDD MOSFET depends slightly on channel length,drain voltage,and gate dielectric permittivity.The model is verified at the end of the paper.

Two-dimensional models of threshold voltage and subthreshold current for symmetrical double-material double-gate strained Si MOSFETs

The two-dimensional models for symmetrical double-material double-gate （DM-DG） strained Si （s-Si） metal-oxide semiconductor field effect transistors （MOSFETs） are presented. The surface potential and the surface electric field ex- pressions have been obtained by solving Poisson＇s equation. The models of threshold voltage and subthreshold current are obtained based on the surface potential expression. The surface potential and the surface electric field are compared with those of single-material double-gate （SM-DG） MOSFETs. The effects of different device parameters on the threshold voltage and the subthreshold current are demonstrated. The analytical models give deep insight into the device parameters design. The analytical results obtained from the proposed models show good matching with the simulation results using DESSIS.

A two-dimensional analytical model for channel potential and threshold voltage of short channel dual material gate lightly doped drain MOSFET

An analytical model for the channel potential and the threshold voltage of the short channel dual-material-gate lightly doped drain （DMG-LDD） metal-oxide-semiconductor field-effect transistor （MOSFET） is presented using the parabolic approximation method. The proposed model takes into account the effects of the LDD region length, the LDD region doping, the lengths of the gate materials and their respective work functions, along with all the major geometrical parameters of the MOSFET. The impact of the LDD region length, the LDD region doping, and the channel length on the channel potential is studied in detail. Furthermore, the threshold voltage of the device is calculated using the minimum middle channel potential, and the result obtained is compared with the DMG MOSFET threshold voltage to show the improvement in the threshold voltage roll-off. It is shown that the DMG-LDD MOSFET structure alleviates the problem of short channel effects （SCEs） and the drain induced barrier lowering （DIBL） more efficiently. The proposed model is verified by comparing the theoretical results with the simulated data obtained by using the commercially available ATLASTM 2D device simulator.

Double-gate tunnel field-effect transistor:Gate threshold voltage modeling and extraction

The tunnel field-effect transistor(TFET) is a potential candidate for the post-CMOS era.As one of the most important electrical parameters of a device,double gate TFET(DG-TFET) gate threshold voltage was studied.First,a numerical simulation study of transfer characteristic and gate threshold voltage in DG-TFET was reported.Then,a simple analytical model for DG-TFET gate threshold voltage VTG was built by solving quasi-two-dimensional Poisson equation in Si film.The model as a function of the drain voltage,the Si layer thickness,the gate length and the gate dielectric was discussed.It is shown that the proposed model is consistent with the simulation results.This model should be useful for further investigation of performance of circuits containing TFETs.

A two-dimensional threshold voltage analytical model for metal-gate/high-k/SiO_2 /Si stacked MOSFETs

In this paper the influences of the metal-gate and high-k/SiO 2 /Si stacked structure on the metal-oxide-semiconductor field-effect transistor（MOSFET） are investigated.The flat-band voltage is revised by considering the influences of stacked structure and metal-semiconductor work function fluctuation.The two-dimensional Poisson＇s equation of potential distribution is presented.A threshold voltage analytical model for metal-gate/high-k/SiO 2 /Si stacked MOSFETs is developed by solving these Poisson＇s equations using the boundary conditions.The model is verified by a two-dimensional device simulator,which provides the basic design guidance for metal-gate/high-k/SiO 2 /Si stacked MOSFETs.

A two-dimensional analytical modeling for channel potential and threshold voltage of short channel triple material symmetrical gate Stack(TMGS) DG-MOSFET

In the present work, a two-dimensional（2D） analytical framework of triple material symmetrical gate stack（TMGS）DG-MOSFET is presented in order to subdue the short channel effects. A lightly doped channel along with triple material gate having different work functions and symmetrical gate stack structure, showcases substantial betterment in quashing short channel effects to a good extent. The device functioning amends in terms of improved exemption to threshold voltage roll-off, thereby suppressing the short channel effects. The encroachments of respective device arguments on the threshold voltage of the proposed structure are examined in detail. The significant outcomes are compared with the numerical simulation data obtained by using 2D ATLAS;device simulator to affirm and formalize the proposed device structure.

漏源电压对SiC MOSFET阈值电压准确测量影响的研究

相较于Si器件,SiC MOSFET近界面氧化物陷阱区域更广,界面态陷阱密度高出2个数量级,大量陷阱不断俘获或释放电荷,导致阈值电压(Vth)随时间波动较大,因而Vth的准确重复测量成为难题。标准中阈值电压测量采用预处理的方法,保证每次测量时陷阱电荷状态的一致性,但标准中未考虑漏源电压影响预处理填充后的陷阱状态,导致阈值电压测试误差。针对该问题,首先通过测量不同漏源电压脉冲影响下的转移曲线,显示不同源漏电压对阈值电压的影响;然后,基于瞬态电流法分析了漏源电压对陷阱电荷状态的影响;进而,分析了漏源电压影响陷阱的机理;最后对比了不同漏源电压对阈值电压测量的影响。实验表明,漏源电压影响栅漏间电场正负,进而影响陷阱填充或释放电荷,导致阈值电压漂移。测量阈值电压时使用较小漏源电压可提高测量准确性,减小可靠性实验由测试因素造成的误差。

基于CEEMDAN和小波包分解的闸门振动信号降噪研究

针对闸门监测振动信号去噪问题,提出基于CEEMDAN(经验模态分解)和小波包分解的闸门振动信号降噪算法,通过采用CEEMDAN和小波包分解方法进行信号去噪,可以有效处理水电站泄洪闸门振动信号中受到的外部干扰。CEEMDAN方法能够将信号分解成多个本征模态函数(IMF),每个IMF代表不同频率的振动成分,使得外部干扰和真实信号成分可以分离。随后,小波包分解能够将每个IMF进一步分解成不同尺度和频率的子频带,这有助于更准确地定位和分离干扰成分。对每个子频带应用阈值去噪技术,可以有效去除噪声,保留真实信号。由测试结果可知,该算法能很好地剔除闸门振动信号中的无用噪声,有效提高闸门振动信号的准确性。

脉冲对InGaZnO薄膜晶体管性能的影响

超大尺寸IGZO(InGaZnO)产品在高温高湿(50℃/80%)信赖性评价中易发生异常显示不良(Abnormal Display,AD)。其不良原因主要是集成栅极驱动电路(Gate Driver On Array,GOA)的关键器件M2转移特性曲线(IDS-VGS)在评价中发生了严重正移。本文通过脉冲实验,模拟GOA关键器件M2的实际工作环境,重现了转移特性曲线严重正移的不良现象。通过设置不同的脉冲实验,揭示了造成不良的主要影响因素:M2器件关闭时,漏极与源极之间的压差VDS过大,使IGZO膜层内的氧空位V+O在电场作用下同时向IGZO与GI(Gate Insulator)的边界及源极端迁移,由于氧空位V+O对电子的捕获作用,最终导致转移特性曲线发生正移,并发现迁移的氧空位V+O经过加热后可以复原。此外,在不改变IGZO成膜条件下,通过减小M2器件关闭时的VDS压差,导入超大尺寸IGZO产品,高温高湿信赖性评价2000 h未发生AD不良。

Positive gate-bias temperature instability of ZnO thin-film transistor

The positive gate-bias temperature instability of a radio frequency （RF） sputtered ZnO thin-film transistor （ZnO TFT） is investigated. Under positive gate-bias stress, the saturation drain current and OFF-state current decrease, and the threshold voltage shifts toward the positive direction. The stress amplitude and stress temperature are considered as important factors in threshold-voltage instability, and the time dependences of threshold voltage shift under various bias temperature stress conditions could be described by a stretched-exponential equation. Based on the analysis of hysteresis behaviors in current- voltage and capacitance-voltage characteristics before and after the gate-bias stress, it can be clarified that the threshold- voltage shift is predominantly attributed to the trapping of negative charge carriers in the defect states located at the gate- dielectric/channel interface.

An Improved SOI CMOS Technology Based Circuit Technique for Effective Reduction of Standby Subthreshold Leakage

Silicon-on-insulator (SOI) CMOS technology is a very attractive option for implementing digital integrated circuits for low power applications. This paper presents migration of standby subthreshold leakage control technique from a bulk CMOS to SOI CMOS technology. An improved SOI CMOS technology based circuit technique for effective reduction of standby subthreshold leakage power dissipation is proposed in this paper. The proposed technique is validated through design and simulation of a one-bit full adder circuit at a temperature of 27℃, supply voltage, VDD of 0.90 V in 120 nm SOI CMOS technology. Existing standby subthreshold leakage control techniques in CMOS bulk technology are compared with the proposed technique in SOI CMOS technology. Both the proposed and existing techniques are also implemented in SOI CMOS technology and compared. Reduction in standby subthreshold leakage power dissipation by reduction factors of 54x and 45x foraone-bit full adder circuit was achieved using our proposed SOI CMOS technology based circuit technique in comparison with existing techniques such as MTCMOS technique and SCCMOS technique respectively in CMOS bulk technology. Dynamic power dissipation was also reduced significantly by using this proposed SOI CMOS technology based circuit technique. Standby subthreshold leakage power dissipation and dynamic power dissipation were also reduced significantly using the proposed circuit technique in comparison with other existing techniques, when all circuit techniques were implemented in SOI CMOS technology. All simulations were performed using Microwindver 3.1 EDA tool.

Hot-carrier degradation for 90 nm gate length LDD- NMOSFET with ultra-thin gate oxide under low gate voltage stress

The hot-carrier degradation for 90 nm gate length lightly-doped drain （LDD） NMOSFET with ultra-thin （1.4 nm） gate oxide under the low gate voltage （LGV） （at Vg = Vth, where Yth is the threshold voltage） stress has been investigated. It is found that the drain current decreases and the threshold voltage increases after the LGV （Vg = Vth） stress. The results are opposite to the degradation phenomena of conventional NMOSFET for the case of this stress. By analysing the gate-induced drain leakage （GIDL） current before and after stresses, it is confirmed that under the LGV stress in ultra-short gate LDD-NMOSFET with ultra-thin gate oxide, the hot holes are trapped at interface in the LDD region and cannot shorten the channel to mask the influence of interface states as those in conventional NMOSFET do, which leads to the different degradation phenomena from those of the conventional NMOS devices. This paper also discusses the degradation in the 90 nm gate length LDD-NMOSFET with 1.4 nm gate oxide under the LGV stress at Yg = Yth with various drain biases. Experimental results show that the degradation slopes （n） range from 0.21 to 0.41. The value of n is less than that of conventional MOSFET （0.5 - 0.6） and also that of the long gate length LDD MOSFET （- 0.8）.

基于电流型CMOS的n变量函数分解新算法及电路设计

电流型电路具有功耗低、速度快的特点,是当今集成电路研究的一个热点.文章基于阈算术代数系统,改进了非相交分解算法;设计了电流型互补金属氧化物半导体(complementary metal oxide semiconductor, CMOS)的异或门电路,并利用改进后的新算法,将n变量函数分解成3变量函数,实现了任意n变量函数电路.模拟测试证明所设计的电路结构简单,且具有正确的逻辑功能.

激光损伤阈值测量装置同步触发模块研究

损伤阈值测量装置是强激光技术的重要技术指标,主要用于强激光光学元件的研制和测试,而同步触发模块作为模块之间时序的控制器,是研制损伤阈值测量装置的关键技术之一。介绍了一种用于激光损伤阈值测量装置的同步触发模块及方法。设计了基于现场可编程门阵列(field programmable gate array,FPGA)为主控芯片的硬件方案,通过上位机操控软件设置同步触发参数,来控制各路输出同步信号的宽度和各路信号之间的时序,可极大提高同步触发的精度和效率。通过实验验证,同步脉冲信号之间的调节精度为2 ns,同步脉冲信号的最小宽度为10 ns,满足激光损伤阈值测量装置的要求。

栅极偏置对SiC MOSFET总剂量效应的影响及加固

文章针对总剂量效应造成的MOSFET阈值漂移问题,使用1 200 V SiC MOSFET进行辐照试验,对栅极偏压和辐照后高温栅极偏置退火对阈值漂移的影响和原理进行了研究。通过中带电压法分析发现,造成阈值电压负向漂移的主要原因是辐照产生的空穴被近界面陷阱俘获。通过对不同栅极氧化层退火条件制备的SiC MOSFET试验和分析,得出了当使用氮化气体退火进行总剂量效应加固时,需要折中考虑对沟道迁移率的影响;在5%氮化气体体积分数、1 300℃下退火60 min的条件下制备出来的SiC MOSFET沟道迁移率较高,并且抗总剂量效应能力较强。

MOS管X射线照射损伤的恢复研究

在通讯设备制造行业中,X射线作为一种无损检测技术有着广泛的应用,相关从业者可通过X射线检测来判别电子元器件中是否存在裂纹、空洞、异物、内部位移和焊接桥联等内部缺陷。但是在实际生产测试中发现,X射线照射也会对半导体器件的性能产生一定的负面影响。研究了X射线照射对MOS管的照射损伤,并探究了不同温度下退火对X射线照射损伤的恢复程度。模拟了严苛条件下的X射线照射过程,用110 kV、60μA的X射线对MOS管进行长时间的照射,测试其在照射前后阈值电压的数值变化;在25~220℃下对其进行退火实验并测试退火后其阈值电压的数值变化,证明了200℃及以上是有效的退火温度,并对实验结果进行初步的分析讨论。

基于BP神经网络的碳化硅MOSFET栅极老化监测方法研究

针对碳化硅MOSFET运行工况复杂、易造成器件栅极老化、影响电力系统可靠性的问题,提出一种基于BP神经网络的碳化硅MOSFET栅极老化监测方法。以碳化硅MOSFET的阈值电压和体二极管通态压降作为栅极老化的敏感表征参数,设计、搭建测试实验平台,获取变测量条件下的电参数值,结合BP神经网络提取健康器件与老化器件样本数据间的特征差异,充分挖掘器件的可靠性信息。实验结果表明:该方法可对碳化硅MOSFET的栅极老化状态进行较为准确的检测和评估。

栅氧化层及界面电荷对SiC MOSFET阈值电压稳定性的影响

阈值电压不稳定是SiC MOSFET的一个主要问题,而栅氧化层及界面电荷是引起器件阈值电压不稳定的关键因素。结合三角波电压扫描法和中带电压法提取了SiC MOSFET中的栅氧化层陷阱电荷面密度、界面陷阱电荷面密度和可动电荷面密度随应力时间的变化量,总结了三种电荷面密度变化量在不同应力时间下的变化规律,分析了其对器件阈值电压不稳定性的影响,同时推测了长时间偏压作用下SiC MOSFET阈值电压稳定性的劣化机制。测试结果表明,栅氧化层陷阱电荷面密度、界面陷阱电荷面密度和可动电荷面密度在不同偏压温度下随应力时间的变化规律不同,常温应力下器件阈值电压稳定性劣化主要与栅氧化层陷阱电荷有关,而高温下,则主要与界面陷阱电荷有关。

Flash型FPGA的编程及干扰抑制技术

为了降低Flash型现场可编程门阵列(FPGA)中的Flash开关单元在编程中受到编程干扰对阈值电压的影响,提高驱动能力的一致性,提出了高位宽编程技术与常用的选择管隔离技术相结合来抑制编程干扰的方法。通过高位宽编程技术降低编程过程中栅扰对同一行中Flash开关单元阈值电压的影响;通过选择管隔离技术降低编程过程中漏扰对同一列中Flash开关单元阈值电压的影响;采用NMOS晶体管作为隔离管实现自限制编程,对Flash开关单元的阈值电压进行精确控制。实验结果表明,参照系统等效门数为百万门级Flash型FPGA中的Flash开关阵列形式2 912 bit×480 WL×20 Bank,按最差条件进行479次漏扰测试,Flash开关单元受编程干扰后的阈值电压漂移约为0 V;进行时长为40μs的栅扰测试,Flash开关单元受编程干扰后阈值电压漂移约为0.02 V。