A self-adaptive full asynchronous bi-directional transmission channel for network-on-chips

To improve two shortcomings of conventional network-on-chips,i.e.low utilization rate in channels between routers and excessive interconnection lines,this paper proposes a full asynchronous self-adaptive bi-directional transmission channel.It can utilize interconnection lines and register resources with high efficiency,and dynamically detect the data transmission state between routers through a direction regulator,which controls the sequencer to automatically adjust the transmission direction of the bi-directional channel,so as to provide a flexible data transmission environment.Null convention logic units are used to make the circuit quasi-delay insensitive and highly robust. The proposed bi-directional transmission channel is implemented based on SMIC 0.18μm standard CMOS technology. Post-layout simulation results demonstrate that this self-adaptive bi-directional channel has better performance on throughput,transmission flexibility and channel bandwidth utilization compared to a conventional single direction channel.Moreover,the proposed channel can save interconnection lines up to 30%and can provide twice the bandwidth resources of a single direction transmission channel.The proposed channel can apply to an on-chip network which has limited resources of registers and interconnection lines.

Optimization design of a full asynchronous pipeline circuit based on null convention logic

This paper proposes a new optimization method to improve the performance of a null convention logic asynchronous pipeline.Parallel combinational logic modules in the pipelines can work alternately in null and data cycles by using a parallel processing mode.The complete waiting time for both null and data signals of combinational logic output in previous asynchronous register stage is reduced by decoupling the output from combinational logic modules.Performance penalty brought by null cycle is reduced while the data processing capacity is increased.The novel asynchronous pipeline based on asynchronous full adders with different bit widths as asynchronous combination logic modules is simulated using 0.18-μm CMOS technology.Based on 6 bits asynchronous adder as asynchronous combination logic modules, the simulation result of this new pipeline proposal demonstrates a high throughput up to 72.4% improvement with appropriate power consumption.This indicates the new design proposal is preferable for high-speed as ynchronous designs due to its high throughput and delay-insensitivity.

A full asynchronous serial transmission converter for network-on-chips

Large transmission power consumptions and excessive interconnection lines are two shortcomings which exist in conventional network-on-chips. To improve performance in these areas, this paper proposes a full asynchronous serial transmission converter for network-on-chips. By grouping the parallel data between routers into smaller data blocks, interconnection lines between routers can be greatly reduced, which finally brings about saving of power over- heads in the transmission process. Null convention logic units are used to make the circuit quasi-delay insensitive and highly robust. The proposed serial transmission converter and serial channel are implemented based on SMIC 0.18 μm standard CMOS technology. Results demonstrate that this full asynchronous serial transmission converter can save up to three quarters of the interconnection line resources and also reduce up to two-thirds of the power consumption under 32 bit data widths. The proposed full asynchronous serial transmission converter can apply to the on chip network which is sensitive to area and power.

Quasi Delay-Insensitive High Speed Two-Phase Protocol Asynchronous Wrapper for Network on Chips

For the purpose of solving the shortcomings of low speed and high power consumption of asynchronous wrapper in conventional network on chips,this paper proposes a quasi delay-insensitive high-speed two-phase operation mode asynchronous wrapper.The metastable state in sampling data procedure can be avoided by detecting the write/read signal, which can be used to stop the clock.Empty/full level of the registers can be determined by detecting the pulse signal of the two-phase asynchronous register,and then control the wrapper to sample input/output data.Sender wrapper and receiver wrapper consist of C elements and threshold gates,which ensure the quasi delay-insensitive characteristics and enhance the robustness.Simulations under different technology corners are implemented based on SMIC 0.18μm standard CMOS. Sender wrapper and receiver wrapper allow synchronous modules to work at the speed of 3.08 GHz and 2.98 GHz respectively with average dynamic power consumption of 1.727 mW and 1.779 mW.Its advantages of high-throughput,low-power, scalability and robustness make it a viable option for high-speed low-power interconnection of network-on-chip.

Design of a novel RTD-based three-variable universal logic gate

Traditional CMOS technology faces some fundamental physical limitations. Therefore, it has become very important for the integrated circuit industry to continue to develop modem devices and new design methods. The threshold logic gate has attracted much attention because of its powerful logic function. The resonant tunneling diode （RTD） is well suited for imple- menting the threshold logic gate because of its high-speed switching capability, negative differential resistance （NDR） charac- teristic, and functional versatility. In this paper, based on the Reed-Muller （RM） algebraic system, a novel method is proposed to convert three-variable non-threshold functions to the XOR of multiple threshold functions, which is simple and has a program- mable implementation. With this approach, all three-variable non-threshold functions can be presented by the XOR of two threshold functions, except for two special functions. On this basis, a novel three-variable universal logic gate （ULG3） is proposed, composed of two RTD-based universal threshold logic gates （UTLG） and an RTD-based three-variable XOR gate （XOR3）. The ULG3 has a simple structure, and a simple method is presented to implement all three-variable functions using one ULG3. Thus, the proposed ULG3 provides a new efficient universal logic gate to implement RTD-based arbitrary n-variable functions.

Enhancement-mode InAlN/GaN MISHEMT with low gate leakage current

We report an enhancement-mode InAlN/GaN MISHEMT with a low gate leakage current by a thermal oxidation technique under gate.The off-state source-drain current density is as low as～10^（17） A/mm at V_（GS）= 0 V and V_（DS） = 5 V.The threshold voltage is measured to be ＋0.8 V by linear extrapolation from the transfer characteristics.The E-mode device exhibits a peak transconductance of 179 mS/mm at a gate bias of 3.4 V.A low reverse gate leakage current density of 4.9×10^（17） A/mm is measured at V_（GS） =-15 V.