In this paper, the optimization of quantizer’s segment threshold is done. The quantizer is designed on the basis of approximative spline functions. Coefficients on which we form approximative spline functions are cal...In this paper, the optimization of quantizer’s segment threshold is done. The quantizer is designed on the basis of approximative spline functions. Coefficients on which we form approximative spline functions are calculated by minimization mean square error (MSE). For coefficients determined in this way, spline functions by which optimal compressor function is approximated are obtained. For the quantizer designed on the basis of approximative spline functions, segment threshold is numerically determined depending on maximal value of the signal to quantization noise ratio (SQNR). Thus, quantizer with optimized segment threshold is achieved. It is shown that by quantizer model designed in this way and proposed in this paper, the SQNR that is very close to SQNR of nonlinear optimal companding quantizer is achieved.展开更多
An area-efficient CMOS 1-MS/s 10-bit charge-redistribution SAR ADC for battery voltage measure- ment in a SoC chip is proposed. A new DAC architecture presents the benefits of a low power approach without applying the...An area-efficient CMOS 1-MS/s 10-bit charge-redistribution SAR ADC for battery voltage measure- ment in a SoC chip is proposed. A new DAC architecture presents the benefits of a low power approach without applying the common mode voltage. The threshold inverter quantizer （TIQ）-based CMOS Inverter is used as a comparator in the ADC to avoid static power consumption which is attractive in battery-supply application. Sixteen level-up shifters aim at converting the ultra low core voltage control signals to the higher voltage level analog circuit in a 55 nm CMOS process. The whole ADC power consumption is 2.5 mW with a maximum input capaci- tance of 12 pF in the sampling mode. The active area of the proposed ADC is 0.0462 mm2 and it achieves the SFDR and ENOB of 65.6917 dB and 9.8726 bits respectively with an input frequency of 200 kHz at 1 MS/s sampling rate.展开更多
基金Serbian Ministry of Education and Science through Mathematical Institute of Serbian Academy of Sciences and Arts(Project III44006)Serbian Ministry of Education and Science(Project TR32035)
文摘In this paper, the optimization of quantizer’s segment threshold is done. The quantizer is designed on the basis of approximative spline functions. Coefficients on which we form approximative spline functions are calculated by minimization mean square error (MSE). For coefficients determined in this way, spline functions by which optimal compressor function is approximated are obtained. For the quantizer designed on the basis of approximative spline functions, segment threshold is numerically determined depending on maximal value of the signal to quantization noise ratio (SQNR). Thus, quantizer with optimized segment threshold is achieved. It is shown that by quantizer model designed in this way and proposed in this paper, the SQNR that is very close to SQNR of nonlinear optimal companding quantizer is achieved.
基金supported by the National Natural Science Foundation of China(No.60736030)the Research Program of Science and Technology Commission of Shanghai(No.11110707100)the National 02 Key Special Program of China(No.2009ZX02305-005)
文摘An area-efficient CMOS 1-MS/s 10-bit charge-redistribution SAR ADC for battery voltage measure- ment in a SoC chip is proposed. A new DAC architecture presents the benefits of a low power approach without applying the common mode voltage. The threshold inverter quantizer （TIQ）-based CMOS Inverter is used as a comparator in the ADC to avoid static power consumption which is attractive in battery-supply application. Sixteen level-up shifters aim at converting the ultra low core voltage control signals to the higher voltage level analog circuit in a 55 nm CMOS process. The whole ADC power consumption is 2.5 mW with a maximum input capaci- tance of 12 pF in the sampling mode. The active area of the proposed ADC is 0.0462 mm2 and it achieves the SFDR and ENOB of 65.6917 dB and 9.8726 bits respectively with an input frequency of 200 kHz at 1 MS/s sampling rate.
