Noise analysis and measurement of time delay and integration charge coupled device

Time delay and integration （TDI） charge coupled device （CCD） noise sets a fundamental limit on image sensor performance, especially under low illumination in remote sensing applications. After introducing the complete sources of CCD noise, we study the effects of TDI operation mode on noise, and the relationship between different types of noise and number of the TDI stage. Then we propose a new technique to identify and measure sources of TDI CCD noise employing mathematical statistics theory, where theoretical analysis shows that noise estimated formulation converges well. Finally, we establish a testing platform to carry out experiments, and a standard TDI CCD is calibrated by using the proposed method. The experimental results show that the noise analysis and measurement methods presented in this paper are useful for modeling TDI CCDs.

Efficiency analysis of numerical integrations for finite element substructure in real-time hybrid simulation

Finite element（FE） is a powerful tool and has been applied by investigators to real-time hybrid simulations（RTHSs）. This study focuses on the computational efficiency, including the computational time and accuracy, of numerical integrations in solving FE numerical substructure in RTHSs. First, sparse matrix storage schemes are adopted to decrease the computational time of FE numerical substructure. In this way, the task execution time（TET） decreases such that the scale of the numerical substructure model increases. Subsequently, several commonly used explicit numerical integration algorithms, including the central difference method（CDM）, the Newmark explicit method, the Chang method and the Gui-λ method, are comprehensively compared to evaluate their computational time in solving FE numerical substructure. CDM is better than the other explicit integration algorithms when the damping matrix is diagonal, while the Gui-λ（λ = 4） method is advantageous when the damping matrix is non-diagonal. Finally, the effect of time delay on the computational accuracy of RTHSs is investigated by simulating structure-foundation systems. Simulation results show that the influences of time delay on the displacement response become obvious with the mass ratio increasing, and delay compensation methods may reduce the relative error of the displacement peak value to less than 5% even under the large time-step and large time delay.

Design and implementation of high speed TDI CCD timing-driven circuits

The time delay integration charge coupled device(TDI CCD)is the key component in remote sensing systems.The paper analyzes the structure and the working principles of the device according to a customized TDI CCD chip.Employing the special clock resources and large-scale phase locked logic(PLL)in field-programmable gate arrays(FPGA),a timing-driven approach is proposed,using which all timing signals including reset gate,horizontal and vertical timing signals,are implemented in one chip.This not only reduces printed circuit board(PCB)space,but also enhances the portability of the system.By studying and calculating CCD parameters thoroughly,load capacity and power consumption,package,etc,are compared between various candidates chips,and detailed comparison results are also listed in table.Experimental results show that clock generator and driving circuit satisfy the requirements of high speed TDI CCD.

Photonic microwave true time delays for phased array antennas using a 49 GHz FSR integrated optical micro-comb source[Invited]

We demonstrate significantly improved performance of a microwave true time delay line based on an integrated optical frequency comb source. The broadband micro-comb(over 100 nm wide) features a record low free spectral range(FSR) of 49 GHz, resulting in an unprecedented record high channel number(81 over the C band)—the highest number of channels for an integrated comb source used for microwave signal processing. We theoretically analyze the performance of a phased array antenna and show that this large channel count results in a high angular resolution and wide beam-steering tunable range. This demonstrates the feasibility of our approach as a competitive solution toward implementing integrated photonic true time delays in radar and communications systems.

A dynamic range extension scheme applied to a TDI CMOS image sensor

A dynamic range extension scheme applied to a time delay integration （TDI） CMOS image sensor （CIS） is presented. Two types of pixels with higher and lower conversion gain are adopted in the pixel array, which are suitable for capturing images in low and high illumination respectively. By fusing the two kinds of pixels＇ output signals in the process of TDI accumulation, a high dynamic range image can be achieved. Compared with the traditional multiple integration technique, no photoelectrons generated during the exposure time are discarded by the reset operation, and thus a higher level of signal-to-noise ratio （SNR） can be retained. A prototype chip with an 8 × 8 pixel array is implemented in a 0.18 μm CIS process, and the pixel size is 15 × 15 μm2. Test results show that a 76 dB dynamic range can be achieved in 8-stage TDI mode, when the SNR boost can reach 7.26 dB at 90.8 lux.

High-stage analog accumulator for TDI CMOS image sensors

The impact of the parasitic phenomenon on the performance of the analog accumulator in TDI CMOS image sensor is analyzed and resolved. A 128-stage optimized accumulator based on 0.18-μm one-poly four-metal 3.3 V CMOS technology is designed and simulated. A charge injection effect from the top plate sampling is em- ployed to compensate the un-eliminated parasitics based on the accumulator with a decoupling switch, and then a calibration circuit is designed to restrain the mismatch and Process, Voltage and Temperature （PVT） variations. The post layout simulation indicates that the improved SNR of the accumulator upgrades from 17.835 to 21.067 dB, while an ideal value is 21.072 dB. In addition, the linearity of the accumulator is 99.62%. The simulation results of two extreme cases and Monte Carlo show that the mismatch and PVT variations are restrained by the calibration circuit. Furthermore, it is promising to design a higher stage accumulator based on the proposed structure.