A 5-bit time to digital converter using time to voltage conversion and integrating techniques for agricultural products analysis by Raman spectroscopy

Time to digital converter(TDC)is a key block for time-gated single photon avalanche diode(SPAD)arrays for Raman spectroscopy that applicable in the agricultural products and food analysis.In this paper a new dual slope time to digital converter that employs the time to voltage conversion and integrating techniques for digitizing the time interval input signals is presented.The reference clock frequency of the TDC is 100 MHz and the input range is theoretically unlimited.The proposed converter features high accuracy,very small average error and high linear range.Also this converter has some advantages such as low circuit complexity,low power consumption and low sensitive to the temperature,power supply and process changes(PVT)compared with the time to digital converters that used preceding conversion techniques.The proposed converter uses an indirect time to digital conversion method.Therefore,our converter has the appropriate linearity without extra elements.In order to evaluate the proposed idea,an integrating time to digital converter is designed in 0.18 lm CMOS technology and was simulated by Hspice.Comparison of the theoretical and simulation results confirms the proposed TDC operation;therefore,the proposed converter is very convenient for applications which have average speed and low variations in the signal amplitude such as biomedical signals.

A high SFDR 6-bit 20-MS/s SAR ADC based on time-domain comparator

This paper presents a 6-bit 20-MS/s high spurious-free dynamic range（SFDR） and low power successive approximation register analog to digital converter（SAR ADC） for the radio-frequency（RF） transceiver frontend, especially for wireless sensor network（WSN） applications.This ADC adopts the modified common-centroid symmetry layout and the successive approximation register reset circuit to improve the linearity and dynamic range. Prototyped in a 0.18-μm 1P6M CMOS technology,the ADC performs a peak SFDR of 55.32 dB and effective number of bits（ENOB） of 5.1 bit for 10 MS/s.At the sample rate of 20 MS/s and the Nyquist input frequency,the 47.39-dB SFDR and 4.6-ENOB are achieved.The differential nonlinearity（DNL） is less than 0.83 LSB and the integral nonlinearity（INL） is less than 0.82 LSB.The experimental results indicate that this SAR ADC consumes a total of 522μW power and occupies 0.98 mm^2.