Graphic processing units （GPUs） have been widely recognized as cost-efficient co-processors with acceptable size, weight, and power consumption. However, adopting GPUs in real-time systems is still challenging, due ...Graphic processing units （GPUs） have been widely recognized as cost-efficient co-processors with acceptable size, weight, and power consumption. However, adopting GPUs in real-time systems is still challenging, due to the lack in framework for real-time analysis. In order to guarantee real-time requirements while maintaining system utilization ~in modern heterogeneous systems, such as multicore multi-GPU systems, a novel suspension-based k-exclusion real-time locking protocol and the associated suspension-aware schedulability analysis are proposed. The proposed protocol provides a synchronization framework that enables multiple GPUs to be efficiently integrated in multicore real-time systems. Comparative evaluations show that the proposed methods improve upon the existing work in terms of schedulability.展开更多
We propose a novel hybrid phase-locked loop （PLL） architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a...We propose a novel hybrid phase-locked loop （PLL） architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a wide-band single-path PLL and a narrow-band dual-path PLL in a transient state and a steady state, respectively, by changing the loop bandwidth according to the gain of voltage controlled oscillator （VCO） and the resister of the loop filter. The hybrid PLL is implemented in a 0.18-μm complementary metal oxide semiconductor （CMOS） process with a total die area of 1.4×0.46 mm2. The measured results exhibit a reference spur level of lower than -73 dB with a reference frequency of 10 MHz and a settling time of 20 μs with 40 MHz frequency jump at 2 GHz. The total power consumption of the hybrid PLL is less than 27 mW with a supply voltage of 1.8 V.展开更多
Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to abo...Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.展开更多
A fast-locking, low-jitter, phase-locked loop （PLL） with a simple phase-frequency detector is proposed. The phase-frequency detector is composed of only two XOR gates. It simultaneously achieves low jitter and short...A fast-locking, low-jitter, phase-locked loop （PLL） with a simple phase-frequency detector is proposed. The phase-frequency detector is composed of only two XOR gates. It simultaneously achieves low jitter and short locking time. The voltage-controlled oscillator within the PLL consists of four-stage ring oscillators which are coupled to each other and oscillate with the same frequency and a phase shift of 45. The PLL is fabricated in 0. 1Stem CMOS technology. The measured phase noise of the PLL output at 500kHz offset from the 5GHz center frequency is - 102.6dBc/Hz. The circuit exhibits a capture range of 280MHz and a low RMS jitter of 2.06ps. The power dissipation excluding the output buffers is only 21.6roW at a 1.8V supply.展开更多
Passively mode-locked fiber lasers emit femtosecond pulse trains with excellent short-term stability. The quantum-limited timing jitter of a free running femtosecond erbium-doped fiber laser working at room temperatur...Passively mode-locked fiber lasers emit femtosecond pulse trains with excellent short-term stability. The quantum-limited timing jitter of a free running femtosecond erbium-doped fiber laser working at room temperature is considerably below one femtosecond at high Fourier frequency. The ultrashort pulse train with ultralow timing jitter enables absolute time-of-flight measurements based on a dual-comb implementation, which is typically composed of a pair of optical frequency combs generated by femtosecond lasers. Dead-zone-free absolute distance measurement with sub-micrometer precision and kHz update rate has been routinely achieved with a dual-comb configuration, which is promising for a number of precision manufacturing applications, from large step-structure measurements prevalent in microelectronic profilometry to three coordinate measurements in large-scale aerospace manufacturing and shipbuilding. In this paper, we first review the sub-femtosecond precision timing jitter characterization methods and approaches for ultralow timing jitter mode-locked fiber laser design. Then, we provide an overview of the state-of-the-art dual-comb absolute ranging technology in terms of working principles, experimental implementations, and measurement precisions. Finally, we discuss the impact of quantum-limited timing jitter on the dual-comb ranging precision at a high update rate. The route to highprecision dual-comb range finder design based on ultralow jitter femtosecond fiber lasers is proposed.展开更多
基金supported by the National Natural Science Foundation of China under Grant No.61003032/F020207
文摘Graphic processing units （GPUs） have been widely recognized as cost-efficient co-processors with acceptable size, weight, and power consumption. However, adopting GPUs in real-time systems is still challenging, due to the lack in framework for real-time analysis. In order to guarantee real-time requirements while maintaining system utilization ~in modern heterogeneous systems, such as multicore multi-GPU systems, a novel suspension-based k-exclusion real-time locking protocol and the associated suspension-aware schedulability analysis are proposed. The proposed protocol provides a synchronization framework that enables multiple GPUs to be efficiently integrated in multicore real-time systems. Comparative evaluations show that the proposed methods improve upon the existing work in terms of schedulability.
基金supported by the National Natural Science Foundation of China(Grant No.61307128)the National Basic Research Program of China(GrantNo.2010CB327505)+1 种基金the Specialized Research Found for the Doctoral Program of Higher Education of China(Grant No.20131101120027)the Basic Research Foundation of Beijing Institute of Technology of China(Grant No.20120542015)
文摘We propose a novel hybrid phase-locked loop （PLL） architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a wide-band single-path PLL and a narrow-band dual-path PLL in a transient state and a steady state, respectively, by changing the loop bandwidth according to the gain of voltage controlled oscillator （VCO） and the resister of the loop filter. The hybrid PLL is implemented in a 0.18-μm complementary metal oxide semiconductor （CMOS） process with a total die area of 1.4×0.46 mm2. The measured results exhibit a reference spur level of lower than -73 dB with a reference frequency of 10 MHz and a settling time of 20 μs with 40 MHz frequency jump at 2 GHz. The total power consumption of the hybrid PLL is less than 27 mW with a supply voltage of 1.8 V.
基金Supported by the Tsinghua National Laboratory for Information Science and Technology(TNList)Cross-Discipline Foundationthe National Science and Technology Major Project(No.2010ZX03006-003-01)
文摘Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.
文摘A fast-locking, low-jitter, phase-locked loop （PLL） with a simple phase-frequency detector is proposed. The phase-frequency detector is composed of only two XOR gates. It simultaneously achieves low jitter and short locking time. The voltage-controlled oscillator within the PLL consists of four-stage ring oscillators which are coupled to each other and oscillate with the same frequency and a phase shift of 45. The PLL is fabricated in 0. 1Stem CMOS technology. The measured phase noise of the PLL output at 500kHz offset from the 5GHz center frequency is - 102.6dBc/Hz. The circuit exhibits a capture range of 280MHz and a low RMS jitter of 2.06ps. The power dissipation excluding the output buffers is only 21.6roW at a 1.8V supply.
基金supported by National Natural Science Foundation of China (Grant Nos.61475162,61675150,and 61535009)Tianjin Natural Science Foundation (Grant No.18JCYBJC16900)Tianjin Research Program of Application Foundation and Advanced Technology (Grant No.17JCJQJC43500)
文摘Passively mode-locked fiber lasers emit femtosecond pulse trains with excellent short-term stability. The quantum-limited timing jitter of a free running femtosecond erbium-doped fiber laser working at room temperature is considerably below one femtosecond at high Fourier frequency. The ultrashort pulse train with ultralow timing jitter enables absolute time-of-flight measurements based on a dual-comb implementation, which is typically composed of a pair of optical frequency combs generated by femtosecond lasers. Dead-zone-free absolute distance measurement with sub-micrometer precision and kHz update rate has been routinely achieved with a dual-comb configuration, which is promising for a number of precision manufacturing applications, from large step-structure measurements prevalent in microelectronic profilometry to three coordinate measurements in large-scale aerospace manufacturing and shipbuilding. In this paper, we first review the sub-femtosecond precision timing jitter characterization methods and approaches for ultralow timing jitter mode-locked fiber laser design. Then, we provide an overview of the state-of-the-art dual-comb absolute ranging technology in terms of working principles, experimental implementations, and measurement precisions. Finally, we discuss the impact of quantum-limited timing jitter on the dual-comb ranging precision at a high update rate. The route to highprecision dual-comb range finder design based on ultralow jitter femtosecond fiber lasers is proposed.
