Employing Two ‘Sandwich Delay’ Mechanisms to Enhance Predictability of Embedded Systems Which Use Time-Triggered Co-Operative Architectures

In many real-time resource-constrained embedded systems, highly-predictable system behavior is a key design requirement. The “time-triggered co-operative” (TTC) scheduling algorithm provides a good match for a wide range of low-cost embedded applications. As a consequence of the resource, timing, and power constraints, the implementation of such algorithm is often far from trivial. Thus, basic implementation of TTC algorithm can result in excessive levels of task jitter which may jeopardize the predictability of many time-critical applications using this algorithm. This paper discusses the main sources of jitter in earlier TTC implementations and develops two alternative implementations – based on the employment of “sandwich delay” (SD) mechanisms – to reduce task jitter in TTC system significantly. In addition to jitter levels at task release times, we also assess the CPU, memory and power requirements involved in practical implementations of the proposed schedulers. The paper concludes that the TTC scheduler implementation using “multiple timer interrupt” (MTI) technique achieves better performance in terms of timing behavior and resource utilization as opposed to the other implementation which is based on a simple SD mechanism. Use of MTI technique is also found to provide a simple solution to “task overrun” problem which may degrade the performance of many TTC systems.

D-scheduler:A scheduler in time-triggered distributed system through decoupling dependencies between tasks and messages

Time-triggered architecture,as a mainstream design of the distributed real-time system,has been successfully applied in the aerospace,automotive and mechanical industries.However,time-triggered scheduling is a challenging NP-hard problem.There are few studies that could quickly solve the scheduling problem of large distributed time-triggered systems.To solve this problem,a communication affinity parameter is defined in this paper to describe the degree of bias of the shaper task towards sending or receiving messages.Based on this,an innovative task-message decoupling model named D-scheduler is built to reduce the computation complexity of the scheduling problem in large-scale systems.Additionally,we provide mathematical proof that our model is a convex optimization that is easy to solve with existing computational tools.Our experiments substantiate the efficacy of the D-scheduler.It dramatically reduces the scheduling complexity of large-scale real-time systems with a small loss of solving space compared to the federal scheduler.

Real-time and reliability analysis of time-triggered CAN-bus

Real-time performance and reliability are two most important issues in applications of time-triggered controller area network （CAN） bus systems at present. A scheduling matrix of time-triggered CAN-bus system is established using average-loading algorithm. Periodic messages are guaranteed to transmit without delay by distributing independent transmission windows within the system matrix. Considering the traditional CAN-bus transmission mechanism and the time-triggered feature, an algorithm is improved to calculate the worst-case delay of event-triggered messages in time-triggered CAN-bus systems. The failure probability is calculated for event-triggered messages whose worst-case delay exceeds their deadlines. Different levels of redundant structures of CAN-bus circuits are analyzed and the maintenance management is proposed to improve the system reliability. Finally, the reliabilities of different structures are calculated and the influences of maintenance on the system reliability are analyzed.

Time-triggered State-machine Reliable Software Architecture for Micro Turbine Engine Control

Time-triggered （TT） embedded software pattern is well accepted in aerospace industry for its high reliability. Fi-nite-state-machine （FSM） design method is widely used for its high efficiency and predictable behavior. In this paper, the time-triggered and state-machine combination software architecture is implemented for a 25 kg thrust micro turbine engine （MTE） used for unmanned aerial vehicle （UAV） system; also model-based-design development workflow for airworthiness software directive DO-178B is utilized. Experimental results show that time-triggered state-machine software architecture and development method could shorten the system development time, reduce the system test cost and make the turbine engine easily comply with the airworthiness rules.

Communication Resource Planning Algorithm Based on Time Triggered DIMA Architecture

Traditional scheduling algorithms for avionics communication have the shortcoming of messages accumulation,the efficiency and reliability of the service can be improved by combining the distributed integrated modular avionics(DIMA)system with a time trigger mechanism.To further improve the utilization of system resources,the static scheduling algorithm of time triggered service is studied.By making the time trigger message schedule dispersedly,the stabilities of both the available time slots for the event triggered messages and the system will be improved.An improved two-dimensional bin packing algorithm is also presented to achieve the above-mentioned purpose with an extra benefit of better delay performance.

M/S Controller Area Network(CAN) System Using Shared-Clock Scheduler

The Controller Area Network (CAN) is a well established control network for automotive and automation control applications. Time-Triggered Controller Area Network (TTCAN) is a recent development which introduces a session layer,for message scheduling,to the existing CAN standard,which is a two layer standard comprising of a physical layer and a data link layer. TTCAN facilitates network communication in a time-triggered fashion,by introducing a Time Division Multiple Access style communication scheme. This allows deterministic network behavior,where maximum message latency times can be quantified and guaranteed. In order to solve the problem of determinate time latency and synchronization among several districted units in one auto panel CAN systems,this paper proposed a prototype design implementation for a shared-clock scheduler based on PIC18F458 MCU. This leads to improved CAN system performance and avoid the latency jitters and guarantee a deterministic communication pattern on the bus. The real runtime performance is satisfied.