For time-of-flight(TOF)light detection and ranging(LiDAR),a three-channel high-performance transimpedance amplifier(TIA)with high immunity to input load capacitance is presented.A regulated cascade(RGC)as the input st...For time-of-flight(TOF)light detection and ranging(LiDAR),a three-channel high-performance transimpedance amplifier(TIA)with high immunity to input load capacitance is presented.A regulated cascade(RGC)as the input stage is at the core of the complementary metal oxide semiconductor(CMOS)circuit chip,giving it more immunity to input photodiode detectors.A simple smart output interface acting as a feedback structure,which is rarely found in other designs,reduces the chip size and power consumption simultaneously.The circuit is designed using a 0.5μm CMOS process technology to achieve low cost.The device delivers a 33.87 dB?transimpedance gain at 350 MHz.With a higher input load capacitance,it shows a-3 dB bandwidth of 461 MHz,indicating a better detector tolerance at the front end of the system.Under a 3.3 V supply voltage,the device consumes 5.2 mW,and the total chip area with three channels is 402.8×597.0μm2(including the test pads).展开更多
This work presents a high-gain broadband inverter-based cascode transimpedance amplifier fabricated in a 65-nm CMOS process.Multiple bandwidth enhancement techniques,including input bonding wire,input series on-chip i...This work presents a high-gain broadband inverter-based cascode transimpedance amplifier fabricated in a 65-nm CMOS process.Multiple bandwidth enhancement techniques,including input bonding wire,input series on-chip inductive peak-ing and negative capacitance compensation,are adopted to overcome the large off-chip photodiode capacitive loading and the miller capacitance of the input device,achieving an overall bandwidth enhancement ratio of 8.5.The electrical measure-ment shows TIA achieves 58 dBΩup to 12.7 GHz with a 180-fF off-chip photodetector.The optical measurement demonstrates a clear open eye of 20 Gb/s.The TIA dissipates 4 mW from a 1.2-V supply voltage.展开更多
A 10 Gb/s OEIC（optoelectronic integrated circuit）optical receiver front-end has been studied and fabricated based on theφ-76 mm GaAs PHEMT process;this is the first time that a limiting amplifier（LA）has been desi...A 10 Gb/s OEIC（optoelectronic integrated circuit）optical receiver front-end has been studied and fabricated based on theφ-76 mm GaAs PHEMT process;this is the first time that a limiting amplifier（LA）has been designed and realized using depletion mode PHEMT.An OEIC optical receiver front-end mode composed of an MSM photodiode and a current mode transimpedance amplifier（TIA）has been established and optimized by simu- lation software ATLAS.The photodiode has a bandwidth of 10 GHz,a capacitance of 3 fF/μm and a photosensitive area of 50×50μm^2.The whole chip has an area of 1511×666μm^2.The LA bandwidth is expanded by spiral inductance which has been simulated by software HFSS.The chip area is 1950×1910μm^2 and the measured results demonstrate an input dynamic range of 34 dB（10–500 mVpp）with constant output swing of 500 mVpp.展开更多
文摘For time-of-flight(TOF)light detection and ranging(LiDAR),a three-channel high-performance transimpedance amplifier(TIA)with high immunity to input load capacitance is presented.A regulated cascade(RGC)as the input stage is at the core of the complementary metal oxide semiconductor(CMOS)circuit chip,giving it more immunity to input photodiode detectors.A simple smart output interface acting as a feedback structure,which is rarely found in other designs,reduces the chip size and power consumption simultaneously.The circuit is designed using a 0.5μm CMOS process technology to achieve low cost.The device delivers a 33.87 dB?transimpedance gain at 350 MHz.With a higher input load capacitance,it shows a-3 dB bandwidth of 461 MHz,indicating a better detector tolerance at the front end of the system.Under a 3.3 V supply voltage,the device consumes 5.2 mW,and the total chip area with three channels is 402.8×597.0μm2(including the test pads).
基金supported in part by the National NaturalScience Foundation of China under Grant 62074074in part by Natural Science Foundation of Guangdong Province under Grant 2021A1515011266in part by the Science and Technology Plan of Shenzhen under Grants JCYJ20190809142017428 and JCYJ20200109141225025。
文摘This work presents a high-gain broadband inverter-based cascode transimpedance amplifier fabricated in a 65-nm CMOS process.Multiple bandwidth enhancement techniques,including input bonding wire,input series on-chip inductive peak-ing and negative capacitance compensation,are adopted to overcome the large off-chip photodiode capacitive loading and the miller capacitance of the input device,achieving an overall bandwidth enhancement ratio of 8.5.The electrical measure-ment shows TIA achieves 58 dBΩup to 12.7 GHz with a 180-fF off-chip photodetector.The optical measurement demonstrates a clear open eye of 20 Gb/s.The TIA dissipates 4 mW from a 1.2-V supply voltage.
基金supported by the National Key Laboratory of Monolithic Integrated Circuits and Modules Foundation of China(No.9140C1406020708)
文摘A 10 Gb/s OEIC（optoelectronic integrated circuit）optical receiver front-end has been studied and fabricated based on theφ-76 mm GaAs PHEMT process;this is the first time that a limiting amplifier（LA）has been designed and realized using depletion mode PHEMT.An OEIC optical receiver front-end mode composed of an MSM photodiode and a current mode transimpedance amplifier（TIA）has been established and optimized by simu- lation software ATLAS.The photodiode has a bandwidth of 10 GHz,a capacitance of 3 fF/μm and a photosensitive area of 50×50μm^2.The whole chip has an area of 1511×666μm^2.The LA bandwidth is expanded by spiral inductance which has been simulated by software HFSS.The chip area is 1950×1910μm^2 and the measured results demonstrate an input dynamic range of 34 dB（10–500 mVpp）with constant output swing of 500 mVpp.
