A detailed analysis of the stability and flipping dynamics of a delayed exclusive toggle switch is performed. We use forward flux sampling method combined with delayed stochastic simulation algorithm to get the statio...A detailed analysis of the stability and flipping dynamics of a delayed exclusive toggle switch is performed. We use forward flux sampling method combined with delayed stochastic simulation algorithm to get the stationary distribution function, the switching rate, and path- ways, as well as the transition state ensemble. Interestingly, under the influence of time delay, the stationary distribution corresponding to the stable states become narrower and the population in the transition region is significantly enhanced. In addition, the flipping rate increases monotonically with delay. Such findings demonstrate that time delay could reduce the stability of the bistable genetic switch dramatically. Furthermore, the transition pathways, characterized by the difference in the protein numbers and the state of operator, show larger discrepancy between the forward and backward switching process with increas- ing delay, indicating that transcriptional and translational delay can remarkably affect the flipping dynamics. Specifically, for the transition state, the difference in the probability of finding the operator site bound by the two different protein dimers is enlarged by delay, which further illustrates the crucial role of time delay on the stability and switching dynamics of genetic toggle switches.展开更多
This paper considers a model of a recursive neuron whose circuit the author finds interesting, not because of its financial possibility, but because of its surprising electrical behavior. Below, a recursive neuron is ...This paper considers a model of a recursive neuron whose circuit the author finds interesting, not because of its financial possibility, but because of its surprising electrical behavior. Below, a recursive neuron is modeled with excitatory and inhibitory triggering, and simulated using Win Spice. This model is shown to be capable of controlled toggling, and so promises energy-efficient, massively parallel computing.展开更多
Recent digital applications will require highly efficient and high-speed gadgets and it is related to the minimum delay and power consumption.The proposed work deals with a low-power clock pulsed data flip-flop(D flip...Recent digital applications will require highly efficient and high-speed gadgets and it is related to the minimum delay and power consumption.The proposed work deals with a low-power clock pulsed data flip-flop(D flip-flop)using a transmission gate.To accomplish a power-efficient pulsed D flip-flop,clock gating is proposed.The gated clock reduces the unnecessary switching of the transistors in the circuit and thus reduces the dynamic power consumption.The clock gating approach is employed by using an AND gate to disrupt the clock input to the circuit as per the control signal called Enable.Due to this process,the clock gets turned off to reduce power consumption when there is no change in the output.The proposed transmission gate-based pulsed D flip-flop’s performance with clock gating and without clock gating circuit is analyzed.The proposed pulsed D flip-flop power consumption is 1.586μw less than the without clock gated flip-flop.Also,the authors have designed a 3-bit serial-in and parallel-out shift register using the proposed D flip-flop and analyzed the performance.Tanner Electronic Design Automation tool is used to simulate all the circuits with 45 nm technology.展开更多
文摘A detailed analysis of the stability and flipping dynamics of a delayed exclusive toggle switch is performed. We use forward flux sampling method combined with delayed stochastic simulation algorithm to get the stationary distribution function, the switching rate, and path- ways, as well as the transition state ensemble. Interestingly, under the influence of time delay, the stationary distribution corresponding to the stable states become narrower and the population in the transition region is significantly enhanced. In addition, the flipping rate increases monotonically with delay. Such findings demonstrate that time delay could reduce the stability of the bistable genetic switch dramatically. Furthermore, the transition pathways, characterized by the difference in the protein numbers and the state of operator, show larger discrepancy between the forward and backward switching process with increas- ing delay, indicating that transcriptional and translational delay can remarkably affect the flipping dynamics. Specifically, for the transition state, the difference in the probability of finding the operator site bound by the two different protein dimers is enlarged by delay, which further illustrates the crucial role of time delay on the stability and switching dynamics of genetic toggle switches.
基金the National Basic Research Program of China，the National Natural Science Foundation of China，the Fundamental Research Funds for the Central Universities
文摘This paper considers a model of a recursive neuron whose circuit the author finds interesting, not because of its financial possibility, but because of its surprising electrical behavior. Below, a recursive neuron is modeled with excitatory and inhibitory triggering, and simulated using Win Spice. This model is shown to be capable of controlled toggling, and so promises energy-efficient, massively parallel computing.
文摘Recent digital applications will require highly efficient and high-speed gadgets and it is related to the minimum delay and power consumption.The proposed work deals with a low-power clock pulsed data flip-flop(D flip-flop)using a transmission gate.To accomplish a power-efficient pulsed D flip-flop,clock gating is proposed.The gated clock reduces the unnecessary switching of the transistors in the circuit and thus reduces the dynamic power consumption.The clock gating approach is employed by using an AND gate to disrupt the clock input to the circuit as per the control signal called Enable.Due to this process,the clock gets turned off to reduce power consumption when there is no change in the output.The proposed transmission gate-based pulsed D flip-flop’s performance with clock gating and without clock gating circuit is analyzed.The proposed pulsed D flip-flop power consumption is 1.586μw less than the without clock gated flip-flop.Also,the authors have designed a 3-bit serial-in and parallel-out shift register using the proposed D flip-flop and analyzed the performance.Tanner Electronic Design Automation tool is used to simulate all the circuits with 45 nm technology.
