Two-dimensional analysis of the interface state effect on current gain for a 4H-SiC bipolar junction transistor

This paper studies two-dimensional analysis of the surface state effect on current gain for a 4H-SiC bipolar junction transistor （BJT）. Simulation results indicate the mechanism of current gain degradation, which is surface Fermi level pinning leading to a strong downward bending of the energy bands to form the channel of surface electron recombination current. The experimental results are well-matched with the simulation, which is modeled by exponential distributions of the interface state density replacing the single interface state trap. Furthermore, the simulation reveals that the oxide quality of the base emitter junction interface is very important for 4H-SiC BJT performance.

MODEL AND MODELING OF LOW TEMPERATURE CURRENT GAIN OF POLYSILICON EMITTER BIPOLAR TRANSISTORS

A unified model of low temperature current gain of polysilicon emitter bipolar transistors based on effective recombination method is presented, incorporating band-gap narrowing, carrier freezing-out, tunneling of holes through polysilicon/silicon interface oxide layer and reduced mobility mechanism in polysilicon. The modeling results based on this model are in good agreement with experimental data.

A novel 4H-SiC lateral bipolar junction transistor structure with high voltage and high current gain

In this paper, a novel structure of a 4H-SiC lateral bipolar junction transistor （LBJT） with a base tield plate and double RESURF in the drift region is presented. Collector-base junction depletion extension in the base region is restricted by the base field plate. Thin base as well as low base doping of the LBJT therefore can be achieved under the condition of avalanche breakdown. Simulation results show that thin base of 0.32 μm and base doping of 3 × 1017 cm 3 are obtained, and corresponding current gain is as high as 247 with avalanche breakdown voltage of 3309 V when the drift region length is 30 μm. Besides, an investigation of a 4H-SiC vertical BJT （VBJT） with comparable breakdown voltage （3357 V） shows that the minimum base width of 0.25 ~tm and base doping as high as 8 × 10^17 cm^-3 contribute to a maximum current gain of only 128.

Thermal analytic model of current gain for bipolar junction transistor-bipolar static induction transistor compound device

This paper proposes a thermal analytical model of current gain for bipolar junction transistor-bipolar static induction transistor （BJT-BSIT） compound device in the low current operation. It also proposes a best thermal compensating factor to the compound device that indicates the relationship between the thermal variation rate of current gain and device structure. This is important for the design of compound device to be optimized. Finally, the analytical model is found to be in good agreement with numerical simulation and experimental results. The test results demonstrate that thermal variation rate of current gain is below 10% in 25 ℃-85 ℃ and 20% in -55 ℃-25 ℃.

NPN型双极晶体管中子位移损伤差异实验研究

利用西安脉冲反应堆(Xi’an pulsed reactor,XAPR)的稳态中子对NPN型双极晶体管(NPN bipolar junction transistor,NPN-BJT)进行中子辐照实验,开展NPN-BJT不同固定发射极电流I_(E)条件下的中子位移损伤差异研究。研究结果表明:同一I_(E)条件下,集成NPN-BJT与2N2222A NPN-BJT的电流增益退化都随辐照中子注量的增加呈逐渐增强趋势;在同一中子注量辐照下,随双极晶体管固定I_(E)的增大,中子辐射损伤常数K_(τ)降低,中子辐照前后电流增益的变化量减小,晶体管电流增益退化程度减弱,因此在一定范围内,提高固定I_(E)可在一定程度上增强NPN-BJT抗中子辐射能力。

A novel structure of a high current gain 4H-SiC BJT with a buried layer in the base

In this paper, a new structure of a 4H-SiC bipolar junction transistor （BJT） with a buried layer （BL） in the base is presented. The current gain shows an approximately 100% increase compared with that of the conventional structure. This is attributed to the creation of a built-in electric field for the minority carriers to transport in the base which is explained based on 2D device simulations. The optimized design of the buried layer region is also considered by numeric simulations.

Fabrication and characterization of 4H-SiC bipolar junction transistor with double base epilayer

In this paper we report on a novel structure of a 4H-SiC bipolar junction transistor with a double base epilayer that is continuously grown. The measured dc common-emitter current gain is 16.8 at Ic = 28.6 mA （Jc = 183.4 A/cm2）, and it increases with the collector current density increasing. The specific on-state resistance （Rsp-on） is 32.3 mΩ.cm2 and the open-base breakdown voltage reaches 410 V. The emitter N-type specific contact resistance and N＋ emitter layer sheet resistance are 1.7× 10-3 Ω.cm2 and 150 Ω/□, respectively.

一种模拟输出CMOS温度传感器的设计与实现

为了实现片上系统温度监测,设计了一款基于0.18μm CMOS工艺的模拟输出温度传感器,该温度传感器核心部分包括偏置电路和感温电路,辅助部分包括单位增益缓冲器电路和端口静电保护电路。偏置电路采用低压共源共栅电流镜结构,感温电路采用直接堆叠多个PNP管的方式,将外界温度转化为具有负温度系数的线性电压信号。再经过基于轨到轨运算放大器的单位增益缓冲器输出,得到模拟电压输出的温度信号。该温度传感器的结构简单、易于设计,并且具有较大输出电压范围。其中核心部分的面积约为0.056 mm^(2),当电源电压为5 V时,静态电流约为6μA。芯片经过流片,测试结果显示,测量温度范围在-55~120℃时,对应的输出电压为2.6~0.7 V,温度误差在3℃以内。

应用于宽带的AlGaN/GaN MIS-HEMT高效率器件

本文采用等离子体增强原子层沉积(PEALD)生长的SiN_(x)栅介质制备了宽带应用的AlGaN/GaN金属绝缘体半导体高电子迁移率晶体管(MIS-HEMTs),并在直流、小信号及大信号测试中评估了该介质层对器件性能的提升。测试结果表明改进器件具有高质量界面、宽栅极控制范围、良好的电流崩塌控制等优势,并确认了其在超过5 GHz下工作时仍能保持较高的功率附加效率(PAE)。在5 GHz连续波模式下,漏极电压V_(DS)=10 V时,MIS HEMT输出功率密度为1.4 W/mm,PAE可达到74.7%;V_(DS)增加到30 V时,功率密度提升到5.9 W/mm,PAE可保持在63.2%的水平;测试频率增加30 GHz,在相同的输出功率水平下,器件的PAE达到50.4%。同时,高质量栅极介电层还可允许器件承受高的栅极电压摆动:在功率增益压缩6 dB时,栅极电流保持在10^(-4)A/mm。上述结果证实了该SiN_(x)栅介质对器件性能的提升,使其满足宽带应用的高效率、高功率和可靠性要求,为系统和电路的宽带设计提供器件级的保障。

牵引级高压IGBT模块短路特性研究及其优化

介绍了IGBT 3种短路类型,通过优化器件的晶体管增益提高第二类短路能力,以承受更大短路电流的冲击,采取驱动电路栅极电压箝位措施来限制短路状态下的过流。经过设计与工艺优化后的高压IGBT成功通过了短路特性试验,满足轨道交通的应用需求。

商用三端稳压器的中子辐射效应

实验研究了两种型号(CJ79L05011和CJ7905011)的商用三端稳压器在不同负载情况下中子辐射效应,得到了输出电压随中子注量的变化曲线。借助三端稳压器的简化模型,分析认为中子辐射下晶体管放大倍数的减少是造成三端稳压器输出电压变化的关键因素,并理论推导了输出电压和晶体管放大倍数的关系,利用PSPICE软件进行了模拟仿真,结果表明理论曲线和实验现象是基本一致的。

一种低电压、高增益电荷泵

电荷泵在低压电路中扮演着重要的角色。作为片上电荷泵,其面临的主要问题是:电压增益、电压纹波和面积效率。该文提出了一种新型的电荷泵电路,它采用辅助电荷泵、电平转移电路结构来产生不同摆幅的时钟,该时钟被用来驱动开关管的栅极,以有效控制开关管的电导,提高电压增益。由于采用PMOS管作为开关管,传输过程中避免了阈值电压损失。仿真结果显示,与以往文献中提到的电荷泵结构相比,该电荷泵具有更高的电压增益,开启时间短,纹波小,在低压应用环境优势更为突出。

双极型晶体管电流增益温度特性的研究

修正了电流增益表达式。对样品3DK105B在不同温度点下进行测试分析。考虑样品理想因子n随温度的变化、VBE随温度的变化,以及禁带宽度随温度变化对电流增益的影响,对电流增益表达式进行了修正,使修正后的结果更加接近实际测试结果。

微波倍频器的设计与研制

针对微波倍频器的实现途径,介绍了阶跃管倍频和三极管倍频的原理,其中三端非线性电阻微波倍频器可实现有增益倍频,且倍频效率高,稳定性好,在现代通信系统中有着广泛的应用前景。应用ADS软件对倍频电路进行优化仿真,利用集总参数电容和电感对阻抗进行匹配,设计利用晶体三极管通过两次4倍频实现了L波段16倍频,最终成功研制出性能优良的L波段16倍频器,输出功率10.67 dBm,杂波抑制>75 dB,谐波抑制>60 dB,电流仅为120 mA,频谱纯净度较好,温度稳定性较高,能够有效实现倍频功能,满足微波频率源系统的使用要求。

小尺寸双极超β晶体管的TCAD设计与优化

基于TCAD一体化系列工具,实现了小尺寸双极性超β晶圆管芯的工艺级及器件物理特性级的 设计与优化。提出了基区宽度接近90nm层次下的小尺寸双极性超β晶体管的工艺实施方案。经TSUPREM -Ⅳ和MEDICI一体化仿真、参数提取及特性的验证表明,设计方案完全可以达到器件参数的要求。

达林顿硅光电晶体管的光放大特性

通过提高达林顿硅光电晶体管的光电灵敏度， 并用１２Ｖ、０２５Ａ 的小灯泡作为输出发光元件， 在２６５μＷ （即９０ｌｘ） 的红光照射下， 器件可输出光电流１００ｍ Ａ 以上， 输出光功率为２０００μＷ 。

达林顿晶体管中稳定电阻对电流增益及电流分配的影响行为

在达林顿晶体管中,由于稳定电阻的引入,使电流增益和各级管间集电极电流分配关系发生了变化.当稳定电阻很小时会造成电流增益的严重下降。本文对稳定电阻的影响行为进行了定量分析,并提出了电流增益和电流分配不受稳定电阻影响时稳定电阻间比值P、稳定电阻基本值R、基极电流I_B 之间应满足的公式。文中图示的曲线族可供达林顿晶体管设计参考.

基于三极管的CFBR-Ⅱ堆辐射损伤常数测定

为获取CFBR-II堆与其他装置建立辐射损伤等效系数的实验依据,在CFBR-II堆稳态工况下开展典型三极管的辐射损伤常数测定工作。结果表明,硅三极管的辐射损伤常数在4×10-16～6×10-16 cm2之间;对于直流增益与中子注量的线性关系的适用范围,集电极注入电流可以拓展到300 mA。

H_（FE）超低温度系数的硅双极晶体管

随着高可靠电子技术的发展，要求硅双极器件的电流增益Ｈ_（ＦＥ）具有很低的正温度系数．发射区重掺杂引起的禁带变窄效应是常规硅双极晶体管Ｈ_（ＦＥ）具有较高正温度系数的主要原因．为了减小这一正温度系数，结合发射区轻掺杂技术，我们采用了新颖的多晶硅部分发射区、多晶硅发射区和非晶硅发射区等结构，获得了电性能优异的Ｈ_（ＦＥ）超低温度系数的硅双极器件，Ｈ_（ＦＥ）的１２５℃高温上升率和－５５℃低温下降率均小于２０％，有些甚至小于１０％．

基于晶体管测量的中子注量在线实时测量系统

利用晶体管直流放大倍数的倒数与中子注量呈线性关系这一特点,使用晶体管作为在线中子注量测量的探测器,建立了以计算机、GPIB总线、矩阵开关、任意波形发生器、数字示波器等硬件为基础,基于LabVIEW软件平台的中子注量在线实时监测系统。在西安脉冲反应堆中子辐射场中,开展了标定实验研究,建立的中子注量在线实时监测系统实现了空间分布的中子注量实时测量,利用该套系统得到了XAPR和CFBR-Ⅱ的等效损伤系数。