MOS Capacitance-Voltage Characteristics Ⅲ.Trapping Capacitance from 2-Charge-State Impurities

Low-frequency and high-frequency capacitance-voltage curves of Metal-Oxide-Semiconductor Capacitors are presented to illustrate giant electron and hole trapping capacitances at many simultaneously present two-charge-state and one-trapped-carrier, or one-energy-level impurity species. Models described include a donor electron trap and an acceptor hole trap, both donors, both acceptors, both shallow energy levels, both deep, one shallow and one deep, and the identical donor and acceptor. Device and material parameters are selected to simu- late chemically and physically realizable capacitors for fundamental trapping parameter characterizations and for electrical and optical signal processing applications.

MOS Capacitance-Voltage Characteristics:V.Methods to Enhance the Trapping Capacitance

Low-frequency and High-frequency Capacitance-Voltage（C-V） curves of Silicon Metal-Oxide-Semiconductor Capacitors,showing electron and hole trapping at shallow-level dopant and deep-level generation-recombination -trapping impurities,are presented to illustrate the enhancement of the giant trapping capacitances by physical means via device and circuit designs,in contrast to chemical means via impurity characteristics previously reported.Enhancement is realized by masking the electron or/and hole storage capacitances to make the trapping capacitances dominant at the terminals.Device and materials properties used in the computed CV curves are selected to illustrate experimental realizations for fundamental trapping parameter characterizations and for electrical and optical signal processing applications.

MOS Capacitance-Voltage Characteristics:Ⅳ.Trapping Capacitance from 3-Charge-State Impurities

Metal-Oxide-Semiconductor Capacitance-Voltage （MOSCV） characteristics containing giant carrier trapping capacitances from 3-charge-state or 2-energy-level impurities are presented for not-doped, n-doped, p- doped and compensated silicon containing the double-donor sulfur and iron, the double-acceptor zinc, and the amphoteric or one-donor and one-acceptor gold and silver impurities. These impurities provide giant trapping ca- pacitances at trapping energies from 200 to 800 meV （50 to 200 THz and 6 to 1.5 μm）, which suggest potential sub-millimeter, far-infrared and spin electronics applications.

Temperature-Dependent Effect of Near-Interface Traps on SiC MOS Capacitance

A two-dimensional electrical SiC MOS interface model including interface and near-interface traps is established based on the relevant tunneling and interface Shockley–Read–Hall model. The consistency between simulation results and measured data in the different temperatures shows that this interface model can accurately describe the capture and emission performance for near-interface oxide traps, and can well explain the hysteresis-voltage response with increasing temperature, which is intensified by the interaction between deep oxide traps and shallow oxide traps. This also indicates that the near-interface traps result in an increase of threshold-voltage shift in SiC MOSFET with increasing temperature.

MOS Capacitance-Voltage Characteristics Ⅱ.Sensitivity of Electronic Trapping at Dopant Impurity from Parameter Variations

Low-frequency and high-frequency Capacitance-Voltage （C-V） curves of Metal-Oxide- Semiconductor Capacitors （MOSC）, including electron and hole trapping at the dopant donor and acceptor impurities, are presented to illustrate giant trapping capacitances, from 〉 0.01Cox to 〉 10Cox. Five device and materials parameters are varied for fundamental trapping parameter characterization, and electrical and optical signal processing applications. Parameters include spatially constant concentration of the dopant-donor-impurity electron trap, NDD, the ground state electron trapping energy level depth measured from the conduction band edge, Ec - ED, the degeneracy of the trapped electron at the ground state, gD, the device temperature, T, and the gate oxide thickness, xox.

MOS Capacitance-Voltage Characteristics from Electron-Trapping at Dopant Donor Impurity

The capacitance versus DC-voltage formula from electron trapping at dopant impurity centers is de- rived for MOS capacitors by the charge-storage method. Fermi-Dirac distribution and impurity deionization are included in the DC-voltage scale. The low-frequency and high-frequency capacitances, and their differences and derivatives, are computed in the presence of an unlimited source of minority and maj ority carriers. The results show that their difference and their DC-voltage derivatives, are large and readily measurable, hence suitable as a method for characterizing the electronic trapping parameters at dopant impurity centers and for a number of lower power signal processing and device technology monitoring applications.

Modeling on oxide dependent 2DEG sheet charge density and threshold voltage in AlGaN/GaN MOSHEMT

We have developed a physics based analytical model for the calculation of threshold voltage, two dimensional electron gas（2DEG） density and surface potential for Al Ga N/Ga N metal oxide semiconductor high electron mobility transistors（MOSHEMT）. The developed model includes important parameters like polarization charge density at oxide/Al Ga N and Al Ga N/Ga N interfaces, interfacial defect oxide charges and donor charges at the surface of the Al Ga N barrier. The effects of two different gate oxides（Al_2O_3 and HfO_2/ are compared for the performance evaluation of the proposed MOSHEMT. The MOSHEMTs with Al_2O_3 dielectric have an advantage of significant increase in 2DEG up to 1.2 10^（13） cm^2 with an increase in oxide thickness up to 10 nm as compared to HfO_2 dielectric MOSHEMT. The surface potential for HfO_2 based device decreases from 2 to –1.6 e V within10 nm of oxide thickness whereas for the Al_2O_3 based device a sharp transition of surface potential occurs from 2.8to –8.3 e V. The variation in oxide thickness and gate metal work function of the proposed MOSHEMT shifts the threshold voltage from negative to positive realizing the enhanced mode operation. Further to validate the model,the device is simulated in Silvaco Technology Computer Aided Design（TCAD） showing good agreement with the proposed model results. The accuracy of the developed calculations of the proposed model can be used to develop a complete physics based 2DEG sheet charge density and threshold voltage model for Ga N MOSHEMT devices for performance analysis.