An oxide filled extended trench gate super junction MOSFET structure

This paper proposes an oxide filled extended trench gate super junction （SJ） MOSFET structure to meet the need of higher frequency power switches application. Compared with the conventional trench gate SJ MOSFET, new structure has the smaller input and output capacitances, and the remarkable improvements in the breakdown voltage, on-resistance and switching speed. Furthermore, the SJ in the new structure can be realized by the existing trench etching and shallow angle implantation, which offers more freedom to SJ MOSFET device design and fabrication.

基于载流子抽取模型的Trench Gate/Field-stop IGBT驱动器有源箝位功能分析

针对Trench gate/Field-stop IGBT结构特有的关断过程中集电极电流下降率不可控问题,引入了载流子抽取模型来模拟器件关断过程中的集电极电流下降阶段器件内部载流子的动态行为特性,并以此为基础分析了驱动器为适应Trench gate/Field-Stop IGBT结构这种关断特性而引入的有源箝位功能的作用机理,验证了载流子抽取模型在器件级与电路级交互作用分析中的实用性,为后续实现器件与电路的最佳匹配奠定了基础。

A low on-resistance triple RESURF SOI LDMOS with planar and trench gate integration

A low on-resistance （Ron,sp） integrable silicon-on-insulator （SOI） n-channel lateral double-diffused metal-oxide-semiconductor （LDMOS） is proposed and its mechanism is investigated by simulation. The LDMOS has two features： the integration of a planar gate and an extended trench gate （double gates （DGs））; and a buried P-layer in the N-drift region, which forms a triple reduced surface field （RESURF） （TR） structure. The triple RESURF not only modulates the electric field distribution, but also increases N-drift doping, resulting in a reduced specific on-resistance （Ron,sp） and an improved breakdown voltage （BV） in the off-state. The DGs form dual conduction channels and, moreover, the extended trench gate widens the vertical conduction area, both of which further reduce the Ron,sp. The BV and Ron,sp are 328 V and 8.8 mΩ·cm^2, respectively, for a DG TR metal-oxide semiconductor field-effect transistor （MOSFET） by simulation. Compared with a conventional SOI LDMOS, a DG TR MOSFET with the same dimensional device parameters as those of the DG TR MOSFET reduces Ron,sp by 59% and increases BV by 6%. The extended trench gate synchronously acts as an isolation trench between the high-voltage device and low-voltage circuitry in a high-voltage integrated circuit, thereby saving the chip area and simplifying the fabrication processes.

Ultralow turnoff loss dual-gate SOI LIGBT with trench gate barrier and carrier stored layer

A novel ultralow turnoff loss dual-gate silicon-on-insulator （SOI） lateral insulated gate bipolar transistor （LIGBT） is proposed. The proposed SOI LIGBT features an extra trench gate inserted between the p-well and n-drift, and an n-type carrier stored （CS） layer beneath the p-well. In the on-state, the extra trench gate acts as a barrier, which increases the cartier density at the cathode side of n-drift region, resulting in a decrease of the on-state voltage drop （Von）. In the off-state, due to the uniform carder distribution and the assisted depletion effect induced by the extra trench gate, large number of carriers can be removed at the initial turnoff process, contributing to a low turnoff loss （Eoff）. Moreover, owing to the dual-gate field plates and CS layer, the carrier density beneath the p-well can greatly increase, which further improves the tradeoff between Eoff and Von. Simulation results show that Eoff of the proposed SOI LIGBT can decrease by 77% compared with the conventional trench gate SOI LIGBT at the same Von of 1.1 V.

Trench gate GaN IGBT with controlled hole injection efficiency

In this paper,a novel trench gate gallium nitride(GaN)insulated gate bipolar transistor(GaN IGBT),in which the collector is divided into multiple regions to control the hole injection efficiency,is designed and theoretically studied.The incorporation of a P+/P-multi-region alternating structure in the collector region mitigates hole injection within the collector region.When the device is in forward conduction,the conductivity modulation effect results in a reduced storage of carriers in the drift region.As a result,the number of carriers requiring extraction during device turn-off is minimized,leading to a faster turn-off speed.The results illustrate that the GaN IGBT with controlled hole injection efficiency(CEH GaN IGBT)exhibits markedly enhanced performance compared to conventional GaN IGBT,showing a remarkable 42.2%reduction in turn-off time and a notable 28.5%decrease in turn-off loss.

Low switching loss and increased short-circuit capability split-gate SiC trench MOSFET with p-type pillar

A split-gate SiC trench gate MOSFET with stepped thick oxide, source-connected split-gate(SG), and p-type pillar(ppillar) surrounded thick oxide shielding region(GSDP-TMOS) is investigated by Silvaco TCAD simulations. The sourceconnected SG region and p-pillar shielding region are introduced to form an effective two-level shielding, which reduces the specific gate–drain charge(Q_(gd,sp)) and the saturation current, thus reducing the switching loss and increasing the short-circuit capability. The thick oxide that surrounds a p-pillar shielding region efficiently protects gate oxide from being damaged by peaked electric field, thereby increasing the breakdown voltage(BV). Additionally, because of the high concentration in the n-type drift region, the electrons diffuse rapidly and the specific on-resistance(Ron,sp) becomes smaller.In the end, comparing with the bottom p~+ shielded trench MOSFET(GP-TMOS), the Baliga figure of merit(BFOM,BV~2/R_(on,sp)) is increased by 169.6%, and the high-frequency figure of merit(HF-FOM, R_(on,sp) × Q_(gd,sp)) is improved by310%, respectively.

一种抗辐射Trench型N 30 V MOSFET器件设计

由于Trench结构在降低元胞单元尺寸、提升沟道密度和消除JFET区电阻等方面的优势,Trench型MOSFET已广泛应用于低压产品领域。在研究抗辐射机理和抗辐射加固技术的基础上,设计了一款新型抗辐射Trench型N30VMOSFET器件。实验结果显示,产品击穿电压典型值达42V,特征导通电阻为51mΩ·mm^(2)。在^(60)Co γ射线100krad(Si)条件下,器件阈值电压漂移仅为-0.3V,漏源漏电流从34nA仅上升到60nA。采用能量为2006MeV、硅中射程为116μm、线性能量传输(LET)值为75.4MeV·cm^(2)/mg的^(118)Ta离子垂直入射该器件,未发生单粒子事件。

A low on-resistance SOI LDMOS using a trench gate and a recessed drain

An integrable silicon-on-insulator （SOl） power lateral MOSFET with a trench gate and a recessed drain （TGRD MOSFET） is proposed to reduce the on-resistance. Both of the trench gate extended to the buried oxide （BOX） and the recessed drain reduce the specific on-resistance （Ron, sp） by widening the vertical conduction area and shortening the extra current path. The trench gate is extended as a field plate improves the electric field distribution. Breakdown voltage （BV） of 97 V and Ron, sp of 0.985 mf2-cm2 （l/os = 5 V） are obtained for a TGRD MOSFET with 6.5/xm half-cell pitch. Compared with the trench gate SOI MOSFET （TG MOSFET） and the conventional MOSFET, Ron＇ sp of the TGRD MOSFET decreases by 46% and 83% at the same BV, respectively. Compared with the SOI MOSFET with a trench gate and a trench drain （TGTD MOSFET）, BV of the TGRD MOSFET increases by 37% at the same Ron,sp.

An improved trench gate super-junction IGBT with double emitter

An improved trench gate super-junction insulated-gate bipolar transistor is presented. The improved structure contains two emitter regions. The first emitter region of the device works as the conventional structure,which can absorb both the electron current and hole current. The second emitter on the top of the p-pillar acts as the hole current diverter, leading to an improved latch-up capability without sacrificing the off-state breakdown voltage（BV） and turn-off loss. The simulation shows that the latch-up limit of the SJ-IGBT increases from 15000 to 28300 A/cm^2 at VGE D10 V, the BV is 810 V, and the turn off loss is 6.5 m J/cm^2 at Von D1.2 V.

A dual-gate and dielectric-inserted lateral trench insulated gate bipolar transistor on a silicon-on-insulator substrate

In this paper, a novel dual-gate and dielectric-inserted lateral trench insulated gate bipolar transistor （DGDI LTIGBT） structure, which features a double extended trench gate and a dielectric inserted in the drift region, is proposed and discussed. The device can not only decrease the specific on-resistance Ron,sp , but also simultaneously improve the temperature performance. Simulation results show that the proposed LTIGBT achieves an ultra-low on-state voltage drop of 1.31 V at 700 A·cm-2 with a small half-cell pitch of 10.5 μm, a specific on-resistance R on,sp of 187 mΩ·mm2, and a high breakdown voltage of 250 V. The on-state voltage drop of the DGDI LTIGBT is 18% less than that of the DI LTIGBT and 30.3% less than that of the conventional LTIGBT. The proposed LTIGBT exhibits a good positive temperature coefficient for safety paralleling to handling larger currents and enhances the short-circuit capability while maintaining a low self-heating effect. Furthermore, it also shows a better tradeoff between the specific on-resistance and the turnoff loss, although it has a longer turnoff delay time.

A novel 4H-SiC trench MOSFET with double shielding structures and ultralow gate-drain charge

A new ultralow gate–drain charge(Q_(GD)) 4 H-SiC trench MOSFET is presented and its mechanism is investigated by simulation. The novel MOSFET features double shielding structures(DS-MOS): one is the grounded split gate(SG), the other is the P+shielding region(PSR). Both the SG and the PSR reduce the coupling effect between the gate and the drain, and transform the most part of the gate–drain capacitance(C_(GD)) into the gate–source capacitance(C_(GS)) and drain–source capacitance(C_(DS)) in series.Thus the C_(GD) is reduced and the proposed DS-MOS obtains ultralow Q_(GD). Compared with the double-trench MOSFET(DT-MOS)and the conventional trench MOSFET(CT-MOS), the proposed DS-MOS decreases the Q_(GD) by 85% and 81%, respectively.Moreover, the figure of merit(FOM), defined as the product of specific on-resistance(R_(on, sp)) and Q_(GD)(R_(on, sp)Q_(GD)), is reduced by 84% and 81%, respectively.

High performance trench MOS barrier Schottky diode with high-k gate oxide

A novel trench MOS barrier Schottky diode（TMBS） device with a high-k material introduced into the gate insulator is reported, which is named high-k TMBS. By simulation with Medici, it is found that the high-k TMBS can have 19.8% lower leakage current while maintaining the same breakdown voltage and forward turn-on voltage compared with the conventional regular trench TMBS.

An ultra-low specific on-resistance trench LDMOS with a U-shaped gate and accumulation layer

An ultra-low specific on-resistance （Ron,sp） oxide trench-type silicon-on-insulator （SOI） lateral double-diffusion metal-oxide semiconductor （LDMOS） with an enhanced breakdown voltage （BV） is proposed and investigated by simulation. There are two key features in the proposed device： one is a U-shaped gate around the oxide trench, which extends from source to drain （UG LDMOS）; the other is an N pillar and P pillar located in the trench sidewall. In the on-state, electrons accumulate along the U-shaped gate, providing a continuous low resistance current path from source to drain. The Ron,sp is thus greatly reduced and almost independent of the drift region doping concentration. In the off-state, the N and P pillars not only enhance the electric field （E-field） strength of the trench oxide, but also improve the E-field distribution in the drift region, leading to a significant improvement in the BV. The BV of 662 V and Ron,sp of 12.4 mΩ.cm2 are achieved for the proposed UG LDMOS. The BV is increased by 88.6% and the Ron,sp is reduced by 96.4%, compared with those of the conventional trench LDMOS （CT LDMOS）, realizing the state-of-the-art trade-off between BV and Ron,sp.

Ultralow Specific on-Resistance Trench MOSFET with a U-Shaped Extended Gate

An ultralow specific on-resistance （Ron,sp） trench metal-oxide-semiconductor field effect transistor （MOSFET） with an improved off-state breakdown voltage （BV） is proposed. It features a U-shaped gate around the drift region and an oxide trench inserted in the drift region （UG MOSFET）. In the on-state, the U-shaped gate induces a high density electron accumulation layer along its sidewall, which provides a low-resistance current path from the source to the drain, realizing an ultralow Ron,sp. The value of Ron,sp is almost independent of the drift doping concentration, and thus the UG MOSFET breaks through the contradiction relationship between R p and the off-state BV. Moreover, the oxide trench folds the drift region, enabling the UG MOSFET to support a high BV with a shortened cell pitch. The UG MOSFET achieves an Ron,sp of 2 mΩ·cm^2 and an improved BV of 216 V, superior to the best existing state-of-the-art transistors at the same BV level

垂直氮化镓沟槽栅极场效应管的优化设计

在传统的氮化镓沟槽栅极场效应管的基础上,通过引入AlGaN层,在异质结界面处形成二维电子气减小器件的导通电阻,并对漂移层的厚度和掺杂浓度进行讨论,使用TCAD软件对器件进行设计优化。最终优化后的漂移层厚度为6μm,掺杂浓度为5×10^(16)cm^(-3)。器件获得了较低的导通电阻R_(on)=0.47 mΩ·cm^(2),较高的击穿电压V_(BR)=2880 V和品质因子FOM=17.6 GW·cm^(-2)。结果显示出了沟槽栅极垂直氮化镓场效应管在高压大电流应用场景下的优势。

具有阶梯掺杂缓冲层的双栅超结LDMOS

具有N型缓冲层的超结横向双扩散金属-半导体场效应晶体管(SJ-LDMOS)结构能够有效抑制传统结构中存在的衬底辅助耗尽效应(SAD)。为进一步优化器件性能,提出了一种具有阶梯型掺杂缓冲层的双栅极SOI基SJ-LDMOS(DG SDB SJ-LDMOS)器件结构。该结构采用沟槽栅极与平面栅极相互结合的形式,在器件内形成两条电流传导路径,其一通过SJ结构中高掺杂的N型区传输,另一条则通过阶梯掺杂缓冲层传输,同时阶梯掺杂缓冲层可以进一步改善表面电场分布,提高器件的耐压。双导通路径提高了SJ层和阶梯掺杂缓冲层的正向电流均匀性,从而有效地降低了器件的导通电阻。仿真结果表明:所提出的器件结构可实现394 V的高击穿电压和10.11 mΩ·cm^(2)的极低比导通电阻,品质因数达到了15.35 MW/cm^(2),与具有相同漂移区长度的SJ-LDMOS相比击穿电压提高了47%,比导通电阻降低了64.8%。

Development of 8-inch Key Processes for Insulated-Gate Bipolar Transistor

Based on the construction of the 8-inch fabricat ion line, advanced process technology of 8-inch wafer, as well as the fourth-generation high-voltage double-diffused metal-oxide semiconductor(DMOS+) insulated-gate bipolar transistor(IGBT) technology and the fifth-generation trench gate IGBT technology, have been developed, realizing a great-leap forward technological development for the manufacturing of high-voltage IGBT from 6-inch to 8-inch. The 1600 A/1.7 kV and 1500 A/3.3 kV IGBT modules have been successfully fabricated, qualified, and applied in rail transportation traction system.

A 4H-SiC trench MOSFET structure with wrap N-type pillar for low oxide field and enhanced switching performance

An optimized silicon carbide(SiC)trench metal-oxide-semiconductor field-effect transistor(MOSFET)structure with side-wall p-type pillar(p-pillar)and wrap n-type pillar(n-pillar)in the n-drain was investigated by utilizing Silvaco TCAD simulations.The optimized structure mainly includes a p+buried region,a light n-type current spreading layer(CSL),a p-type pillar region,and a wrapping n-type pillar region at the right and bottom of the p-pillar.The improved structure is named as SNPPT-MOS.The side-wall p-pillar region could better relieve the high electric field around the p+shielding region and the gate oxide in the off-state mode.The wrapping n-pillar region and CSL can also effectively reduce the specific on-resistance(Ron,sp).As a result,the SNPPT-MOS structure exhibits that the figure of merit(Fo M)related to the breakdown voltage(V_(BR))and Ron,sp(V_(BR)^2R_(on,sp))of the SNPPT-MOS is improved by 44.5%,in comparison to that of the conventional trench gate SJ MOSFET(full-SJ-MOS).In addition,the SNPPT-MOS structure achieves a much fasterwitching speed than the full-SJ-MOS,and the result indicates an appreciable reduction in the switching energy loss.

Ultra-low specific on-resistance vertical double-diffused metal-oxide semiconductor with a high-k dielectric-filled extended trench

An ultra-low specific on-resistance trench gate vertical double-diffused metal-oxide semiconductor with a high-k dielectric-filled extended trench（HK TG VDMOS） is proposed in this paper.The HK TG VDMOS features a high-k（HK） trench below the trench gate.Firstly,the extended HK trench not only causes an assistant depletion of the n-drift region,but also optimizes the electric field,which therefore reduces Ron,sp and increases the breakdown voltage（BV）.Secondly,the extended HK trench weakens the sensitivity of BV to the n-drift doping concentration.Thirdly,compared with the superjunction（SJ） vertical double-diffused metal-oxide semiconductor（VDMOS）,the new device is simplified in fabrication by etching and filling the extended trench.The HK TG VDMOS with BV = 172 V and Ron,sp = 0.85 mΩ·cm2 is obtained by simulation;its Ron,sp is reduced by 67% and 40% and its BV is increased by about 15% and 5%,in comparison with those of the conventional trench gate VDMOS（TG VDMOS） and conventional superjunction trench gate VDMOS（SJ TG CDMOS）.

A 4H-SiC semi-super-junction shielded trench MOSFET: p-pillar is grounded to optimize the electric field characteristics

A 4H-SiC trench gate metal-oxide-semiconductor field-effect transistor(UMOSFET)with semi-super-junction shiel-ded structure(SS-UMOS)is proposed and compared with conventional trench MOSFET(CT-UMOS)in this work.The advantage of the proposed structure is given by comprehensive study of the mechanism of the local semi-super-junction structure at the bottom of the trench MOSFET.In particular,the influence of the bias condition of the p-pillar at the bottom of the trench on the static and dynamic performances of the device is compared and revealed.The on-resistance of SS-UMOS with grounded(G)and ungrounded(NG)p-pillar is reduced by 52%(G)and 71%(NG)compared to CT-UMOS,respectively.Additionally,gate ox-ide in the GSS-UMOS is fully protected by the p-shield layer as well as semi-super-junction structure under the trench and p-base regions.Thus,a reduced electric-field of 2 MV/cm can be achieved at the corner of the p-shield layer.However,the quasi-intrinsic protective layer cannot be formed in NGSS-UMOS due to the charge storage effect in the floating p-pillar,resulting in a large electric field of 2.7 MV/cm at the gate oxide layer.Moreover,the total switching loss of GSS-UMOS is 1.95 mJ/cm2 and is reduced by 18%compared with CT-UMOS.On the contrary,the NGSS-UMOS has the slowest overall switching speed due to the weakened shielding effect of the p-pillar and the largest gate-to-drain capacitance among the three.The proposed GSS-UMOS plays an important role in high-voltage and high-frequency applications,and will provide a valuable idea for device design and circuit applications.