A Statistical Method for Characterizing CMOS Process Fluctuations in Subthreshold Current Mirrors

A novel method to characterize CMOS process fluctuations in subthreshold current mirrors （SCM） is reported. The proposed model is succinct in methodology and calculation complexity compared with previous statistical models. However,it provides favorable estimations of CMOS process fluctuations on the SCM circuit, which makes it promising for engineering applications. The model statistically abstracts physical parameters, which depend on the IC process, into random variables with certain mean values and standard deviations, while aggregating all the random impacts into a discrete martingale. The correctness of the proposed method is experimentally verified on an SCM circuit implemented in an SMIC 0.18μm CMOS 1P6M mixed signal process with a conversion factor of 100 in an input range from 100pA to lμA. The pro- posed theory successfully predicts - 10% of die-to-die fluctuation measured in the experiment, and also suggests the -lmV of threshold voltage standard deviation over a single die,which meets the process parameters suggested by the design kit from the foundry. The deviations between calculated probabilities and measured data are less than 8%. Meanwhile, pertinent suggestions concerning high fluctuation tolerance subthreshold analog circuit design are also made and discussed.

High-Voltage MOSFETs in a 0.5μm CMOS Process

There is growing interest in developing high-voltage MOSFET devices that can be integrated with low-voltage CMOS digital and analog circuits. In this paper,high-voltage nand p-type MOSFETs are fabricated in a commercial 3.3/ 5V 0.5μm n-well CMOS process without adding any process steps using n-well and p-channel stops. High current and highvoltage transistors with breakdown voltages between 23 and 35V for the nMOS transistors with different laydut parameters and 19V for the pMOS transistors are achieved. This paper also presents the insulation technology and characterization results for these high-voltage devices.

A 1.2 V,3.1%3σ-accuracy thermal sensor analog front-end circuit in 12 nm CMOS process

This paper presents a 1.2 V high accuracy thermal sensor analog front-end circuit with 7 probes placed around the microprocessor chip.This analog front-end consists of a BGR(bandgap reference),a DEM(dynamic element matching)control,and probes.The BGR generates the voltages linear changed with temperature,which are followed by the data read out circuits.The superior accuracy of the BGR’s output voltage is a key factor for sensors fabricated via the FinFET digital process.Here,a 4-stage folded current bias structure is proposed,to increase DC accuracy and confer immunity against FinFET process variation due to limited device length and low current bias.At the same time,DEM is also adopted,so as to filter out current branch mismatches.Having been fabricated via a 12 nm FinFET CMOS process,200 chips were tested.The measurement results demonstrate that these analog front-end circuits can work steadily below 1.2 V,and a less than 3.1%3σ-accuracy level is achieved.Temperature stability is 0.088 mV/℃across a range from-40 to 130℃.

Study of CMOS integrated signal processing circuit in capacitive sensors

A CMOS integrated signal processing circuit based on capacitance resonance principle whose structure is simple in capacitive sensors is designed. The waveform of output voltage is improved by choosing bootstrap reference current mirror with initiate circuit, CMOS analogy switch and positive feedback of double-stage inverter in the circuit. Output voltage of this circuit is a symmetric square wave signal. The variation of sensitive capacitance, which is part of the capacitive sensors, can be denoted by the change of output vohage＇s frequency. The whole circuit is designed with 1.5 μm P-weU CMOS process and simulated by PSpice software. Output frequency varies from 261.05 kHz to 47. 93 kHz if capacitance varies in the range of 1PF - 15PF. And the variation of frequency can be easily detected using counter or SCU.

一种CMOS阻抗谱测量电路设计

为了实现待测阻抗实部与虚部的提取,设计了一款基于0.18μm CMOS工艺的阻抗谱测量电路,其通过频率响应分析法在数字域中进行累乘与累加的操作,从而得到阻抗谱。该阻抗谱测量电路由Δ-Σ调制器和数字抽取滤波器等电路组成。相较于传统阻抗谱检测电路而言,该电路采用无运放Δ-Σ调制器结构,能对电流信号进行直接转换,减少了一个跨阻放大器(TIA)和一个跨导放大器(OTA),极大程度地减小了芯片的功耗和面积。仿真结果表明,在2 MHz的采样时钟下,2 kHz的带宽内,调制器的信噪失真比(SNDR)达到66.5 dB,有效位数(ENOB)达到10.75 bit,当电源电压为1.8 V时,电路功耗低至140μW。电路的阻抗谱输出与电流呈现良好线性关系。

基于0.18μm CMOS工艺的低功耗采样保持电路

基于0.18μm CMOS工艺设计了一款用于ADC前端的采样保持电路,电路采用输入缓冲器-采样开关-输出缓冲器三级结构实现。为提高采样保持电路的保持平稳度,设计了信号馈通和时钟馈通消除结构。为改善频率响应,设计了无源负反馈结构并研究了器件参数对电路性能的影响。仿真结果表明,该馈通消除结构能够提升保持阶段的平稳度,负反馈可将增益提升36 dB。该电路在800 MS/s采样率、122.6 MHz正弦波输入条件下,增益为0 dB,3 dB带宽为1 GHz,信号失真比为48 dB,有效位数为7.7 bit。最终版图面积为202μm×195μm,功耗为37.22 mW,实现了低功耗的设计目标。

用于高精度模数转换器的CMOS可变增益放大器

针对工业领域数据采集系统对大摆幅模拟信号精确采样的需求,提出了一种方便与高精度模数转换器(ADC)集成的CMOS可变增益放大器(VGA)。该VGA基于反相放大器结构,在5 V单电源供电的条件下支持最大±10 V信号输入。对传递函数的设计和电路结构的优化可保证VGA高线性度的同时不降低信噪比(SNR)。电路采用TSMC 0.18μm CMOS工艺进行设计并流片,面积为0.23 mm^(2),5 V供电时功耗为1.5 mW。在输入信号1 kHz、采样率200 kS/s条件下,将VGA与16 bit逐次逼近寄存器(SAR)ADC进行联合测试,测试结果表明信噪比达到89.80 dB,总谐波失真(THD)为-102.31 dB。该VGA具有输入范围大、精度高、面积小的特点,为工业信号采集应用提供了高集成度的解决方案。

A novel integrated ultraviolet photodetector based on standard CMOS process

A novel integrated ultraviolet（UV） photodetector has been proposed, which realizes a high UV selectivity by combining a conventional UV-selective photodiode with an extra infrared（IR） photodiode. The IR photodiode is designed for compensating the photocurrent response of the UV photodiode in the infrared band and is 15 times smaller than the UV one. The integrated photodetector has been fabricated in a 0.35 μm standard CMOS technology. Some critical performance indices of this new structure photodetector, such as spectral responsivity, breakdown voltage, quenching waveform, and transient response, are measured and analyzed. Test results show that the complementary UV–IR photodetector has a maximum spectral responsivity of 0.27 A·W-1 at the wavelength of 400 nm. The device has a high UV selectivity of 3000,which is much higher than that of the single UV photodiode.

Δ<i>I_DDQ</i>Testing of a CMOS Digital-to-Analog Converter Considering Process Variation Effects

In this paper, we present the implementation of a built-in current sensor (BICS) which takes into account the increased background current of defect-free circuits and the effects of process variation on ΔIDDQ testing of CMOS data converters. A 12-bit digital-to-analog converter (DAC) is designed as the circuit under test (CUT). The BICS uses frequency as the output for fault detection in CUT. A fault is detected if it causes the output frequency to deviate more than ±10% from the reference frequency. The output frequencies of the BICS for various (MOSIS) model parameters are simulated to check for the effect of process variation on the frequency deviation. A set of eight faults simulating manufacturing defects in CMOS data converters are injected using fault-injection transistors and tested successfully.

与CMOS工艺兼容的硅高速光电探测器模拟与设计

用器件模拟的方法 ,设计了一种与常规 CMOS工艺兼容的硅高速光电探测器 ,该探测器可与 CMOS接收机电路单片集成 ,对该探测器进行了器件模拟研究 ,给出了该探测器的电路模型 .通过 MOSIS(MOS im plem entationsupport project) 0 .35μm COMS工艺制做了该探测器 ,实际测试了该器件的频率响应和波长响应 ,探测器频率响应在 1GHz以上 ,峰值波长响应在 0 .6 9μm.

高动态科学级CMOS相机系统的设计

为了满足全局曝光模式下对高动态范围CMOS相机需求,基于CIS-2521sCMOS器件设计出一个相机系统,通过研究CIS-2521芯片像素读出结构特点和全局曝光模式下驱动时序特点,选用FPGA搭载DDR3作为处理架构,在FPGA内部完成了成像参数控制,sCMOS驱动时序,图像数据采集,图像预处理等SOPC片上一体化设计,并对各个模块功能进行了介绍。设计的相机系统进行成像测试,实现了连续输出50帧/s,2 560×2 160像素,14bit有效深度的高清晰度高动态范围图像,基本满足科学级成像条件的需求。

集成于无源UHF RFID标签的高分辨率CMOS温度传感器

提出一种高分辨率的集成于无源UHF RFID标签的CMOS温度传感器结构。采用时域数字量化的方式,用与绝对温度成正比PTAT(Proportional to Absolute Temperature)电流源和标签内部振荡器构成的PTAT振荡器产生脉冲宽度与温度相关的脉冲信号,作为计数器的时钟信号,在温度-50℃～50℃范围内,脉冲周期从1.841μs～0.426μs;用数字电路对阅读器发送的帧头命令进行处理得到一个宽度为200μs的宽脉冲信号,作为计数器的使能信号,该脉冲的宽度完全不受温度影响;通过采样计数,得到包含温度信息的数字信号。本设计采用0.18μm UMC CMOS工艺,电源电压为1.8 V,直流功耗为789 nW,温度传感器后仿的有效分辨率达到0.332 LSB/℃。

面阵CMOS图像传感器性能测试及图像处理

CMOS图像传感器具有驱动简单、单电源供电、集成度高、功耗低、抗辐射能力强等优点。但是在航天光学遥感领域,CMOS图像传感器应用还不普遍。在该领域亟需大规模、高读出速度、大动态范围的图像传感器,CMOS图像传感器LUPA4000正是这样一款高性能面阵图像传感器,因此,选择LUPA4000作为研究对象,对其缺陷像元、光响应非均匀性、信噪比等性能指标进行测试。测试结果表明存在缺陷像元数量多、光响应非均匀性较大、信噪比较低等问题。根据测试结果采用暗背景扣除、缺陷像元替换、非均匀校正三种方法进行图像处理。对每种方法单独处理和各种方法组合处理的处理效果从图像信噪比和成像图像质量两方面进行分析评估,结果表明:非均匀校正联合缺陷像元替换的处理方法处理效果最佳。

CMOS数字摄象IC及其在视频图象采集中的应用

详细介绍了一种只有集成电路大小的ＣＭＯＳ彩色数字摄象集成电路的内部结构、特点及其在视频图象采集、处理等方面的应用，并给出一种通过ＵＳＢ接口将数字图象送入微机中的应用实例。

新型高速低功耗CMOS动态比较器的特性分析

为了降低sigma-delta模数转换器功耗,针对应用于sigma-delta模数转换器环境的UMC 0.18μm工艺,提出1种由参考电压产生电路、预放大器、锁存器以及用作输出采样器的动态锁存器组成的新型高速低功耗的CMOS预放大锁存比较器。该比较器中输出采样器由传输门和2个反相器组成,可在较大程度上减少该比较器的功耗。电路采用标准UMC0.18μm工艺进行HSPICE模拟。研究结果表明:该比较器在1.8V电源电压下,分辨率为8位,在40MHz的工作频率下,功耗仅为24.4μW,约为同类比较器功耗的1/3。

1.25 Gbps并串转换CMOS集成电路

分析了由超高速易重用单元构造的树型和串行组合结构 ,实现了在输入半速率时钟条件下 1 0路到1路吉比特率并串转换。通过理论推导着重讨论了器件延时和时钟畸变对并串转换的影响 ,指出了解决途径。芯片基于 0 .3 5μm CMOS工艺 ,采用全定制设计 ,芯片面积为 2 4.1 9mm2 。串行数据输出的最高工作速率达到 1 .62 Gbps,可满足不同吉比特率通信系统的要求。在 1 .2 5 Gbps标准速率 ,工作电压 3 .3 V,负载为 5 0 Ω的条件下 ,功耗为 1 74.84m W,输出电压峰 -峰值可达到 2 .42 V,占空比为 49% ,抖动为 3 5 ps rms。测试结果和模拟结果一致 ,表明所设计的电路结构在性能、速度、功耗和面积优化方面的先进性。文中设计的芯片具有广泛应用和产业化前景。

应用于RFID的超低功耗CMOS温度传感器设计

针对融合射频识别（RFID）的无线温度传感器节点设计的需求,采用0.18μm 1P6M台积电CMOS工艺,设计了一种低功耗集成温度传感器。该温度传感器首先将温度信号转换为电压信号,然后通过经压控振荡器将电压信号转换为受温度控制的频率信号,再通过计数器,将频率信号转换为数字信号。传感器电路利用MOS管工作在亚阈值区,并采用动态阈值技术获得超低功耗。测试结果显示：所设计的温度传感器仅占用0.051 mm2,功耗仅为101 n W,在0~100℃范围内误差为-1.5~1.2℃。

基于CMOS图像传感器的压缩感知成像算法

近年来提出的压缩感知理论将信号采样和压缩同时进行,突破了奈奎斯特采样定理的限制,为低采样高分辨率成像提供了可能.为此,提出了一种基于CMOS图像传感器的压缩感知成像算法,采用并行处理策略对CMOS图像传感器A/D转换前的模拟像素矩阵进行压缩采样,减轻了A/D转换模块的负担,大大降低了CMOS图像传感器的功耗,并且该算法实现电路简单.仿真结果表明,所提算法能快速有效地进行测量值的获取,利用TVAL3算法重构的图像主客观质量较好.

基于静态场景下不遮光CMOS摄像头的核辐射探测

CMOS传感器可与X/γ射线直接作用,因此存在利用分布广泛的监控摄像头进行核辐射探测的可能性。本文对静态场景下不遮光CMOS摄像头进行了初步实验验证:将约7.4×108 Bq的99 Tcm放射源置于罗技科技(Logitech)C170摄像头旁不同距离处,在静态场景下分别采集1 000帧视频图像,发现视频图像上产生了异常的随机亮斑。本文提出一种帧间差分、高斯平滑和阈值判断相结合的方法,甄别每帧图像是否含有随机亮斑,并采用TERRA-P多用途个人剂量报警仪进行了对比实验。实验结果表明:可见光图像上叠加的亮斑是由核辐射产生的,且每千帧视频图像中含亮斑帧数与辐射剂量率线性相关,相关系数R=0.99;本文提出的算法可有效甄别静态场景下不遮光CMOS摄像头所采集视频图像中的放射性事件,即实现了对核辐射的探测。未来将进一步优化视频处理算法,期望实现基于公共场所大量监控摄像头的低成本核辐射监测。

CMOS图像实时增强预处理研究及实现

针对CMOS图像传感器固有的不足,本文提出了一种图像增强预处理的算法及实现方法,首先介绍了预处理总体框架,结合实时性、可移植性以及硬件性能的要求,着重讨论图像增强预处理主要功能模块的算法实现,包括伽马校正、色彩插值、色彩校正、色彩空间变化、图像增强、增益控制、对比度调整以及自动曝光等。实验结果表明:该方法有效地改善了图像传感器图像的质量。