A 0.8–4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications is successfully realized by the 130 nm CMOS process. A series of novel methods are proposed in this paper.Two band DCOs...A 0.8–4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications is successfully realized by the 130 nm CMOS process. A series of novel methods are proposed in this paper.Two band DCOs with high frequency resolution are utilized to cover the frequency band of interest, which is as wide as 2.5 to 5 GHz. An overflow counter is proposed to prevent the ＂pulse-swallowing＂ phenomenon so as to significantly reduce the locking time. A NTW-clamp digital module is also proposed to prevent the overflow of the loop control word. A modified programmable divider is presented to prevent the failure operation at the boundary.The measurement results show that the output frequency range of this frequency synthesizer is 0.8–4.2 GHz. The locking time achieves a reduction of 84% at 2.68 GHz. The best in-band and out-band phase noise performances have reached –100 d Bc/Hz, and –125 d Bc/Hz respectively. The lowest reference spur is –58 d Bc.展开更多
为了兼顾非接触式原子力显微镜(noncontact atomic force microscope,NC-AFM)更高谐振频率探针的使用需求,并通过提高控制器精度进而提高NC-AFM分辨率,提出了一种基于探针-样品间原子作用力变化的全数字可调谐NC-AFM高分辨率探针起振系...为了兼顾非接触式原子力显微镜(noncontact atomic force microscope,NC-AFM)更高谐振频率探针的使用需求,并通过提高控制器精度进而提高NC-AFM分辨率,提出了一种基于探针-样品间原子作用力变化的全数字可调谐NC-AFM高分辨率探针起振系统。在Simulink环境下对探针起振系统的控制部分进行了设计,通过现场可编程门阵列(FPGA)实现了鉴相,滤波,锁频等功能;采用压电陶瓷片驱动探针振动,设计了操作便捷的探针座。将不同频率正弦信号提供给设计的起振系统进行功能性验证,实验结果表明,系统可以在20 kHz~50 MHz频率范围内跟踪探针谐振频率;最后使用起振系统成功使商用探针在谐振频率处振动,准确测出了探针的谐振频率及振动幅值,系统频率分辨率达到了0.1 Hz。展开更多
基金Project supported by the National Natural Science Foundation of China(No.61176029)the National Twelve-Five Project(No.513***)
文摘A 0.8–4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications is successfully realized by the 130 nm CMOS process. A series of novel methods are proposed in this paper.Two band DCOs with high frequency resolution are utilized to cover the frequency band of interest, which is as wide as 2.5 to 5 GHz. An overflow counter is proposed to prevent the ＂pulse-swallowing＂ phenomenon so as to significantly reduce the locking time. A NTW-clamp digital module is also proposed to prevent the overflow of the loop control word. A modified programmable divider is presented to prevent the failure operation at the boundary.The measurement results show that the output frequency range of this frequency synthesizer is 0.8–4.2 GHz. The locking time achieves a reduction of 84% at 2.68 GHz. The best in-band and out-band phase noise performances have reached –100 d Bc/Hz, and –125 d Bc/Hz respectively. The lowest reference spur is –58 d Bc.
