A novel CMOS atto-ampere current mirror （AACM） is proposed which reaches the minimum yet reported current range of 0.4 aA. Operation of this circuit is based on the source voltage modulation instead of the conventio...A novel CMOS atto-ampere current mirror （AACM） is proposed which reaches the minimum yet reported current range of 0.4 aA. Operation of this circuit is based on the source voltage modulation instead of the conventionally used gate voltage modulation which interestingly prevents usage of commonly required voltage shifting in those circuits. The proposed circuit has a simple structure prohibiting large chip area consumption which consumes extremely low power of 1.5 μW. It is thus the best choice for ultra low power low voltage （ULPLV） applications. By using a very simple frequency compensation technique, its bandwidth is widened to 15.8 kHz. Simulation results in SMIC （Semiconductor Manufacturing International Corporation） 0.18 μm CMOS technology with Hspice are presented to demonstrate the validation of the proposed current mirror.展开更多
A model of enhancement mode GaAs MESFET (EFET) for low power consumption and low noise applications has been obtained by using a small signal equivalent circuit whose component values are derived from the physical p...A model of enhancement mode GaAs MESFET (EFET) for low power consumption and low noise applications has been obtained by using a small signal equivalent circuit whose component values are derived from the physical parameters and the bias condition. The dependence of the RF performance and DC power consumption on physical, material and technological parameters of EFET is also studied. The optimum range of the physical parameters is given which is useful for the design of active device of ultra low power consumption MMIC.展开更多
With the increase of the clock frequency and silicon integration, power aware computing has become a critical concern in the design of the embedded processor and system-on-chip （SoC）. Dynamic voltage scaling （DVS）...With the increase of the clock frequency and silicon integration, power aware computing has become a critical concern in the design of the embedded processor and system-on-chip （SoC）. Dynamic voltage scaling （DVS） is an effective method for low-power designs. However, traditional DVS methods have two deficiencies. First, they have a conservative safety margin which is not necessary for most of the time. Second, they are exclusively concerned with the critical stage and ignore the significant potential free slack time of the noncritical stage. These factors lead to a large amount of power waste. In this paper, a novel pipeline structure with ultra-low power consumption is proposed. It cuts off the safety margin and takes use of the noncritical stages at the same time. A prototype pipeline is designed in 0.13 μm technology and analyzed. The result shows that a large amount of energy can be saved by using this structure. Compared with the fixed voltage case, 50% of the energy can be saved, and with respect to the traditional adaptive voltage scaling design, 37.8% of the energy can be saved.展开更多
Power consumption is the bottleneck of system performance. Power reduction has become an important issue in digital circuit design, especially for high performance portable devices (such as cell phones, PDAs, etc.). M...Power consumption is the bottleneck of system performance. Power reduction has become an important issue in digital circuit design, especially for high performance portable devices (such as cell phones, PDAs, etc.). Many power reduction techniques have also been proposed from the system level down to the circuit level. High-speed computation has thus become the expected norm from the average user, instead of being the province of the few with access to a powerful mainframe. Power must be added to the portable unit, even when power is available in non-portable applications, the issue of low-power design is becoming critical. Thus, it is evident that methodologies for the design of high-throughput, low-power digital systems are needed. Techniques for low-power operation are shown in this paper, which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. The threshold vol-tages of the MTCMOS devices for both low and high Vth are constructed as the low threshold Vth is approximately 150 - 200 mv whereas the high threshold Vth is managed by varying the thickness of the oxide Tox. Hence we are using different threshold voltages with minimum voltages and hence considered this project as ultra-low power designing.展开更多
From the perspective of development background,concepts and related policies of ultra-low emission,according to work practice,some issues and difficulties that need to be paid attention to in the environmental impact ...From the perspective of development background,concepts and related policies of ultra-low emission,according to work practice,some issues and difficulties that need to be paid attention to in the environmental impact assessment of ultra-low-emission thermal power projects were discussed from the aspects of evaluation criteria,evaluation grade and scope,pollution control technical lines,environmental benefit accounting,and total emission control,and corresponding recommendations were put forward.展开更多
This paper presents the design of a low power LNA with second stage that uses a notch filter for DS-UWB application. The LNA employs a current reuse structure to reduce the power consumption and an active second order...This paper presents the design of a low power LNA with second stage that uses a notch filter for DS-UWB application. The LNA employs a current reuse structure to reduce the power consumption and an active second order notch filter to produce band rejection in the 5 - 6 GHz frequency band. The input reflection coefficient S11 and output reflection S22 are both less than –10 dB. The maximum power gain S21 is 15 dB while the maximum rejection ratio is over –10 dB at 4.8 GHz. The minimum noise figure is 5 dB. The input referred third-order intercept point (IIP3) is –7 dBm at 6 GHz. The power consumption is 6.4 mW from a 1-V power supply.展开更多
This paper presents research on a low power CMOS UWB LNA based on a cascoded common source and current-reused topology. A systematic approach for the design procedure from narrow band to UWB is developed and discussed...This paper presents research on a low power CMOS UWB LNA based on a cascoded common source and current-reused topology. A systematic approach for the design procedure from narrow band to UWB is developed and discussed in detail. The power reduction can be achieved by using body biased technique and current-reused topology. The optimum width of the major transistor device M1 is determined by the power-constraint noise optimization with inner parasitic capacitance between the gate and source terminal. The derivation of the signal amplification S21 by high frequency small signal model is displayed in the paper. The optimum design of the complete circuit was studied in a step by step analysis. The measurements results show that the proposed circuit has superior S11, gain, noise figure, and power consumption. From the measured results, S11 is lower than -12 dB, S22 is lower than -10 dB and forward gain S21 has an average value with 12 dB. The noise figure is from 4 to 5.7 dB within the whole band. The total power consumption of the proposed circuit including the output buffer is 4.6 mW with a supply voltage of 1 V. This work is implemented in a standard TSMC 0.18 μm CMOS process technology.展开更多
文摘A novel CMOS atto-ampere current mirror （AACM） is proposed which reaches the minimum yet reported current range of 0.4 aA. Operation of this circuit is based on the source voltage modulation instead of the conventionally used gate voltage modulation which interestingly prevents usage of commonly required voltage shifting in those circuits. The proposed circuit has a simple structure prohibiting large chip area consumption which consumes extremely low power of 1.5 μW. It is thus the best choice for ultra low power low voltage （ULPLV） applications. By using a very simple frequency compensation technique, its bandwidth is widened to 15.8 kHz. Simulation results in SMIC （Semiconductor Manufacturing International Corporation） 0.18 μm CMOS technology with Hspice are presented to demonstrate the validation of the proposed current mirror.
文摘A model of enhancement mode GaAs MESFET (EFET) for low power consumption and low noise applications has been obtained by using a small signal equivalent circuit whose component values are derived from the physical parameters and the bias condition. The dependence of the RF performance and DC power consumption on physical, material and technological parameters of EFET is also studied. The optimum range of the physical parameters is given which is useful for the design of active device of ultra low power consumption MMIC.
基金supported by the Important National S&T Special Project of China under Grant No.2011ZX01034-002-001-2the Fundamental Research Funds for the Central Universities under Grant No.ZYGX2009J026
文摘With the increase of the clock frequency and silicon integration, power aware computing has become a critical concern in the design of the embedded processor and system-on-chip （SoC）. Dynamic voltage scaling （DVS） is an effective method for low-power designs. However, traditional DVS methods have two deficiencies. First, they have a conservative safety margin which is not necessary for most of the time. Second, they are exclusively concerned with the critical stage and ignore the significant potential free slack time of the noncritical stage. These factors lead to a large amount of power waste. In this paper, a novel pipeline structure with ultra-low power consumption is proposed. It cuts off the safety margin and takes use of the noncritical stages at the same time. A prototype pipeline is designed in 0.13 μm technology and analyzed. The result shows that a large amount of energy can be saved by using this structure. Compared with the fixed voltage case, 50% of the energy can be saved, and with respect to the traditional adaptive voltage scaling design, 37.8% of the energy can be saved.
文摘Power consumption is the bottleneck of system performance. Power reduction has become an important issue in digital circuit design, especially for high performance portable devices (such as cell phones, PDAs, etc.). Many power reduction techniques have also been proposed from the system level down to the circuit level. High-speed computation has thus become the expected norm from the average user, instead of being the province of the few with access to a powerful mainframe. Power must be added to the portable unit, even when power is available in non-portable applications, the issue of low-power design is becoming critical. Thus, it is evident that methodologies for the design of high-throughput, low-power digital systems are needed. Techniques for low-power operation are shown in this paper, which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. The threshold vol-tages of the MTCMOS devices for both low and high Vth are constructed as the low threshold Vth is approximately 150 - 200 mv whereas the high threshold Vth is managed by varying the thickness of the oxide Tox. Hence we are using different threshold voltages with minimum voltages and hence considered this project as ultra-low power designing.
基金Supported by Special Project for Research on Prevention and Control of Air Pollution from Fire Coal in 2018 of Ministry of Ecology and Environment of the People’s Republic of China(2018A030)
文摘From the perspective of development background,concepts and related policies of ultra-low emission,according to work practice,some issues and difficulties that need to be paid attention to in the environmental impact assessment of ultra-low-emission thermal power projects were discussed from the aspects of evaluation criteria,evaluation grade and scope,pollution control technical lines,environmental benefit accounting,and total emission control,and corresponding recommendations were put forward.
文摘This paper presents the design of a low power LNA with second stage that uses a notch filter for DS-UWB application. The LNA employs a current reuse structure to reduce the power consumption and an active second order notch filter to produce band rejection in the 5 - 6 GHz frequency band. The input reflection coefficient S11 and output reflection S22 are both less than –10 dB. The maximum power gain S21 is 15 dB while the maximum rejection ratio is over –10 dB at 4.8 GHz. The minimum noise figure is 5 dB. The input referred third-order intercept point (IIP3) is –7 dBm at 6 GHz. The power consumption is 6.4 mW from a 1-V power supply.
文摘This paper presents research on a low power CMOS UWB LNA based on a cascoded common source and current-reused topology. A systematic approach for the design procedure from narrow band to UWB is developed and discussed in detail. The power reduction can be achieved by using body biased technique and current-reused topology. The optimum width of the major transistor device M1 is determined by the power-constraint noise optimization with inner parasitic capacitance between the gate and source terminal. The derivation of the signal amplification S21 by high frequency small signal model is displayed in the paper. The optimum design of the complete circuit was studied in a step by step analysis. The measurements results show that the proposed circuit has superior S11, gain, noise figure, and power consumption. From the measured results, S11 is lower than -12 dB, S22 is lower than -10 dB and forward gain S21 has an average value with 12 dB. The noise figure is from 4 to 5.7 dB within the whole band. The total power consumption of the proposed circuit including the output buffer is 4.6 mW with a supply voltage of 1 V. This work is implemented in a standard TSMC 0.18 μm CMOS process technology.
