The speed performance and static power dissipation of the ultra-thin-body （UTB） MOSFETs have been comprehensively investigated, with both DC and AC behaviours considered. Source/drain extension width （Lsp） and sil...The speed performance and static power dissipation of the ultra-thin-body （UTB） MOSFETs have been comprehensively investigated, with both DC and AC behaviours considered. Source/drain extension width （Lsp） and silicon film thickness （tsi） are two independent parameters that influence the speed and static power dissipation of UTB siliconon-insulator （SOI） MOSFETs respectively, which can result in great design flexibility. Based on the different effects of physical and geometric parameters on device characteristics, a method to alleviate the contradiction between power dissipated and speed of UTB SOI MOSFETs is proposed. The optimal design regions of tsi and Lsp for low operating power and high performance logic applications are given, which may shed light on the design of UTB SOI MOSFETs.展开更多
This is Part II of a two-part paper that explores the 28-nm UTBB FD-SOI CMOS and the 22-nm Tri-Gate FinFET technology as the better alternatives to bulk transistors especially when the transistor’s architecture is go...This is Part II of a two-part paper that explores the 28-nm UTBB FD-SOI CMOS and the 22-nm Tri-Gate FinFET technology as the better alternatives to bulk transistors especially when the transistor’s architecture is going fully depleted and its size is becoming much smaller, 28-nm and above. Reliability tests of those alternatives are first discussed. Then, a comparison is made between the two alternative transistors comparing their physical properties, electrical properties, and their preferences in different applications.展开更多
Nowadays, transistor technology is going toward the fully depleted architecture;the bulk transistors are becoming more complex in manufacturing as the transistor size is becoming smaller to achieve the high performanc...Nowadays, transistor technology is going toward the fully depleted architecture;the bulk transistors are becoming more complex in manufacturing as the transistor size is becoming smaller to achieve the high performance especially at the node 28 nm. This is the first of two papers that discuss the basic drawbacks of the bulk transistors and explain the two alternative transistors: 28 nm UTBB FD-SOI CMOS and the 22 nm Tri-Gate FinFET. The accompanying paper, Part II, focuses on the comparison between those alternatives and their physical properties, electrical properties, and reliability tests to properly set the preferences when choosing for different mobile media and consumers’ applications.展开更多
SOI LDMOS是SOI高压集成电路的核心器件,而纵向击穿电压是制约其性能的关键。本文首先指出了常规SOI LDMOS纵向耐压低的原因;然后介绍了SOI高压器件纵向耐压理论,分析了该理论中三种改善SOI器件纵向耐压技术(超薄SOI技术、界面电荷技术...SOI LDMOS是SOI高压集成电路的核心器件,而纵向击穿电压是制约其性能的关键。本文首先指出了常规SOI LDMOS纵向耐压低的原因;然后介绍了SOI高压器件纵向耐压理论,分析了该理论中三种改善SOI器件纵向耐压技术(超薄SOI技术、界面电荷技术、低k介质层技术)的工作原理;而后基于这三种技术,对近年来国内外在SOI纵向耐压方面所做的工作进行了分类和总结,分析了各自的优缺点;最后对未来技术的发展进行了展望。展开更多
The importance ofsubstrate doping engineering for extremely thin SOI MOSFETs with ultra-thin buried oxide （ES-UB-MOSFETs） is demonstrated by simulation. A new substrate/backgate doping engineering, lateral non-unifo...The importance ofsubstrate doping engineering for extremely thin SOI MOSFETs with ultra-thin buried oxide （ES-UB-MOSFETs） is demonstrated by simulation. A new substrate/backgate doping engineering, lateral non-uniform dopant distributions （LNDD） is investigated in ES-UB-MOSFETs. The effects of LNDD on device performance, Vt-roll-off, channel mobility and random dopant fluctuation （RDF） are studied and optimized. Fixing the long channel threshold voltage （Vt） at 0.3 V, ES-UB-MOSFETs with lateral uniform doping in the substrate and forward back bias can scale only to 35 nm, meanwhile LNDD enables ES-UB-MOSFETs to scale to a 20 nm gate length, which is 43% smaller. The LNDD degradation is 10% of the carrier mobility both for nMOS and pMOS, but it is canceled out by a good short channel effect controlled by the LNDD. Fixing Vt at 0.3 V, in long channel devices, due to more channel doping concentration for the LNDD technique, the RDF in LNDD controlled ES-UB-MOSFETs is worse than in back-bias controlled ES-UB-MOSFETs, but in the short channel, the RDF for LNDD controlled ES-UB-MOSFET is better due to its self-adaption of substrate doping engineering by using a fixed thickness inner-spacer. A novel process flow to form LNDD is proposed and simulated.展开更多
基金Project supported by the National Natural Science Foundation of China （Grant No 60625403）, the State Key Development Program for Basic Research of China （Grant No 2006CB302701）.
文摘The speed performance and static power dissipation of the ultra-thin-body （UTB） MOSFETs have been comprehensively investigated, with both DC and AC behaviours considered. Source/drain extension width （Lsp） and silicon film thickness （tsi） are two independent parameters that influence the speed and static power dissipation of UTB siliconon-insulator （SOI） MOSFETs respectively, which can result in great design flexibility. Based on the different effects of physical and geometric parameters on device characteristics, a method to alleviate the contradiction between power dissipated and speed of UTB SOI MOSFETs is proposed. The optimal design regions of tsi and Lsp for low operating power and high performance logic applications are given, which may shed light on the design of UTB SOI MOSFETs.
文摘This is Part II of a two-part paper that explores the 28-nm UTBB FD-SOI CMOS and the 22-nm Tri-Gate FinFET technology as the better alternatives to bulk transistors especially when the transistor’s architecture is going fully depleted and its size is becoming much smaller, 28-nm and above. Reliability tests of those alternatives are first discussed. Then, a comparison is made between the two alternative transistors comparing their physical properties, electrical properties, and their preferences in different applications.
文摘Nowadays, transistor technology is going toward the fully depleted architecture;the bulk transistors are becoming more complex in manufacturing as the transistor size is becoming smaller to achieve the high performance especially at the node 28 nm. This is the first of two papers that discuss the basic drawbacks of the bulk transistors and explain the two alternative transistors: 28 nm UTBB FD-SOI CMOS and the 22 nm Tri-Gate FinFET. The accompanying paper, Part II, focuses on the comparison between those alternatives and their physical properties, electrical properties, and reliability tests to properly set the preferences when choosing for different mobile media and consumers’ applications.
基金supported by the Opening Project of Key Laboratory of Microelectronics Devices & Integrated Technology,Institute of Microelectronics the China National S & T Major Project 02
文摘The importance ofsubstrate doping engineering for extremely thin SOI MOSFETs with ultra-thin buried oxide （ES-UB-MOSFETs） is demonstrated by simulation. A new substrate/backgate doping engineering, lateral non-uniform dopant distributions （LNDD） is investigated in ES-UB-MOSFETs. The effects of LNDD on device performance, Vt-roll-off, channel mobility and random dopant fluctuation （RDF） are studied and optimized. Fixing the long channel threshold voltage （Vt） at 0.3 V, ES-UB-MOSFETs with lateral uniform doping in the substrate and forward back bias can scale only to 35 nm, meanwhile LNDD enables ES-UB-MOSFETs to scale to a 20 nm gate length, which is 43% smaller. The LNDD degradation is 10% of the carrier mobility both for nMOS and pMOS, but it is canceled out by a good short channel effect controlled by the LNDD. Fixing Vt at 0.3 V, in long channel devices, due to more channel doping concentration for the LNDD technique, the RDF in LNDD controlled ES-UB-MOSFETs is worse than in back-bias controlled ES-UB-MOSFETs, but in the short channel, the RDF for LNDD controlled ES-UB-MOSFET is better due to its self-adaption of substrate doping engineering by using a fixed thickness inner-spacer. A novel process flow to form LNDD is proposed and simulated.
