Continued scaling of CMOS technology to achieve high performance and low power consumption of semiconductor devices in the complex integrated circuits faces the degradation in terms of electrostatic integrity, short c...Continued scaling of CMOS technology to achieve high performance and low power consumption of semiconductor devices in the complex integrated circuits faces the degradation in terms of electrostatic integrity, short channel effects （SCEs）, leakage currents, device variability and reliability etc. Nowadays, multigate structure has become the promising candidate to overcome these problems. SO1 FinFET is one of the best multigate structures that has gained importance in all electronic design automation （EDA） industries due to its improved short channel effects （SCEs）, because of its more effective gate-controlling capabilities. In this paper, our aim is to ex- plore the sensitivity of underlap spacer region variation on the performance of SOI FinFET at 20 nm channel length. Electric field modulation is analyzed with spacer length variation and electrostatic performance is evalu- ated in terms of performance parameter like electron mobility, electric field, electric potential, sub-threshold slope （SS）, ON current （Ion）, OFF current （/off） and Ion/loll ratio. The potential benefits of SOl FinFET at drain-to-source voltage, liDS = 0.05 V and VDS = 0.7 V towards analog and RF design is also evaluated in terms of intrinsic gain （Av）, output conductance （go）, trans-conductance （gin）, gate capacitance （Cgg）, and cut-off frequency OCT = gm/2πCgg） with spacer region variations.展开更多
文摘Continued scaling of CMOS technology to achieve high performance and low power consumption of semiconductor devices in the complex integrated circuits faces the degradation in terms of electrostatic integrity, short channel effects （SCEs）, leakage currents, device variability and reliability etc. Nowadays, multigate structure has become the promising candidate to overcome these problems. SO1 FinFET is one of the best multigate structures that has gained importance in all electronic design automation （EDA） industries due to its improved short channel effects （SCEs）, because of its more effective gate-controlling capabilities. In this paper, our aim is to ex- plore the sensitivity of underlap spacer region variation on the performance of SOI FinFET at 20 nm channel length. Electric field modulation is analyzed with spacer length variation and electrostatic performance is evalu- ated in terms of performance parameter like electron mobility, electric field, electric potential, sub-threshold slope （SS）, ON current （Ion）, OFF current （/off） and Ion/loll ratio. The potential benefits of SOl FinFET at drain-to-source voltage, liDS = 0.05 V and VDS = 0.7 V towards analog and RF design is also evaluated in terms of intrinsic gain （Av）, output conductance （go）, trans-conductance （gin）, gate capacitance （Cgg）, and cut-off frequency OCT = gm/2πCgg） with spacer region variations.
