A compact and reconfigurable low noise amplifier employing combinational active inductors and composite resistors feedback techniques

A compact and reconfigurable low noise amplifier(LNA)is proposed by combining an input transistor,composite transistors with Darlington configuration as the amplification and output transistor,T-type structure composite resistors instead of a simplex structure resistor,a shunt inductor feedback realized by a tunable active inductor(AI),a shunt inductor peaking technique realized by another tunable AI.The division and collaboration among different resistances in the T-type structure composite resistor realize simultaneously input impedance matching,output impedance matching and good noise performance;the shunt feedback and peaking technique using two tunable AIs not only extend frequency bandwidth and improve gain flatness,but also make the gain and frequency band can be tuned simultaneously by the external bias of tunable AIs;the Darlington configuration of composite transistors provides high gain;furthermore,the adoption of the small size AIs instead of large size passive spiral inductor,and the use of composite resistors make the LNA have a small size.The LNA is fabricated and verified by GaAs/InGaP hetero-junction bipolar transistor(HBT)process.The results show that at the frequency of 7 GHz,the gain S_(21)is maximum and up to 19 dB;the S_(21)can be tuned from 17 dB to 19 dB by tuning external bias of tunable AIs,that is,the tunable amount of S_(21)is 2 dB,and similarly at 8 GHz;the tunable range of 3 dB bandwidth is 1 GHz.In addition,the gain S_(21)flatness is better than 0.4 dB under frequency from 3.1 GHz to 10.6 GHz;the size of the LNA only has 760μm×1260μm(including PADs).Therefore,the proposed strategies in the paper provide a new solution to the design of small size and reconfigurable ultra-wideband(UWB)LNA and can be used further to adjust the variations of gain and bandwidth of radio frequency integrated circuits(RFICs)due to package,parasitic and the variation of fabrication process and temperature.

Wideband CMOS variable gain amplifier with decibel-linear gain control characteristic

This paper presents a wideband variable gain amplifier(VGA) featuring a decibel-linear gain control characteristic. The decibel-linear gain control function is realized using two VGA cells and a control signal converter. The bandwidth is extended by using cascode architecture together with active inductive load. To achieve small parasitic and low area,direct current(DC) coupling is adopted in the circuit while a DC offset cancellation(DCOC) circuit is introduced to cancel the DC offset. Fabricated in a 0.18 μm complementary metal oxide semiconductor(CMOS) process, the chip occupies an area of 0.53 mm×0.48 mm(including pads) and draws a total current of 9 mA from a 1.8 V supply. The measurement results show that the gain of the VGA varies from-40 dB to 18 dB while the control voltage varies from 0 to 1.8 V, resulting in a total gain control range of 58 dB. The 3 dB bandwidth of the VGA is larger than 260 MHz at maximum gain.

A novel reconfigurable variable gain amplifier for a multi-mode multi-band receiver

This paper presents a novel approach for designing a reconfigurable variable gain amplifier（VGA） for the multi-mode multi-band receiver system RF front-end applications.The configuration,which is comprised of gain circuits,control circuit,DC offset cancellation circuit and mode switch circuit is proposed to save die area and power consumption with the function of multi-mode and multi-band through reusing.The VGA is realized in 0.18μm CMOS technology with 1.8 V power supply voltage providing a gain tuning range from 5 to 87 dB when the control voltage varies from 0 to 1.8 V.The 3 dB bandwidth is about 80 MHz for all levels of control voltage（all gains）.Also,the DC offset cancellation circuit can effectively suppress DC offset to a value of less than 40 mV at the output regardless of the input.The overall power consumption is less than 3 mA,and die area is 705×100μm^2.

A CMOS variable gain low-noise amplifier with ESD protection for 5 GHz applications

This paper presents a variable gain low-noise amplifier（VG-LNA） for 5 GHz applications.The effect of the input parasitic capacitance on the inductively degenerated common source LNA＇s input impedance is analyzed in detail.A new ESD and LNA co-design method was proposed to achieve good performance.In addition,by using a simple feedback loop at the second stage of the LNA,continuous gain control is realized.The measurement results of the proposed VG-LNA exhibit 25 dB（-3.3 dB to 21.7 dB） variable gain range,2.8 dB noise figure at the maximum gain and 1 dBm IIP3 at the minimum gain,while the DC power consumption is 9.9 mW under a 1.8 V supply voltage.

5.2 GHz variable-gain amplifier and power amplifier driver for WLAN IEEE 802.11a transmitter front-end

A 5.2 GHz variable-gain amplifier （VGA） and a power amplifier （PA） driver are designed for WLAN IEEE 802.11 a monolithic RFIC. The VGA and the PA driver are implemented in a 50 GHz 0.35 μm SiGe BiCMOS technology and occupy 1.12 × 1.25 mm^2 die area. The VGA with effective temperature compensation is controlled by 5 bits and has a gain range of 34 dB. The PA driver with tuned loads utilizes a differential input, single-ended output topology, and the tuned loads resonate at 5.2 GHz. The maximum overall gain of the VGA and the PA driver is 29 dB with the output third-order intercept point （OIP3） of 11 dBm. The gain drift over the temperature varying from -30 to 85 ℃ converges within ±3 dB. The total current consumption is 45 mA under a 2.85 V power supply.

一种用于5G终端增益可调的低噪声放大器设计

针对无线接收机需要对不同强度信号进行不同程度放大的要求,采用WIN公司的0.15μm GaAs pHEMT工艺设计了一款工作频段为5G通信频段3~5 GHz的可变增益低噪声放大器。该放大器包含两级放大电路,均采用自偏置结构,降低了端口数量,通过调节第二级放大电路的控制电压在0至5 V之间变化,可实现系统增益的连续可调范围约39.3 dB(-3.5~35.8 dB)。放大器版图尺寸为0.94×1.24 mm^(2)。控制电压为0 V时,系统噪声为0.53±0.01 dB,增益为35.5±0.35 dB,中心频点4 GHz处,OP1dB为13.2 dBm, OIP3达到32.7 dBm,表明系统具有良好的线性度。

一种基于电容中和技术的低功耗宽带VGA设计

阐述一种基于电容中和技术的宽带可变增益放大器(VGA),用于高速通信和高分辨率雷达系统。提出的负电容通路有效地拓展了带宽,并在不同的增益设定下实现平坦的带内增益。仿真结果表明,VGA在增益-2.8~49.4dB调节范围内均实现带宽超过4.0GHz。它的功耗在1V的电源电压下为16.5mW,核心电路面积为0.006 mm^(2)。

CMOS Automatic Gain Control Circuit with DC Offset Cancellation for FM/cw Ladar

This paper presented an automatic gain control(AGC) circuit suitable for FM/cw ladar. The proposed architecture was based on two-stage variable gain amplifier(VGA) chain with a novel DC offset canceller circuit, which contained an improved Gilbert cell and a Gm-C feedback loop. To keep the VGA with a linearity in dB characteristic, an improved exponential gain control circuit was introduced. The AGC was implemented in 0.18 μm standard CMOS process. Simulation and measurement results verified that its gain ranged from-20 dB to 30 dB, and bandwidth ranged from 100 kHz to 10 MHz. Its power consumption was 19.8 mW under a voltage supply of 3.3 V.

用于宽带任意波发生器的可变增益放大器

在宽带任意波发生器(AWG)研制中,一个重要的挑战来自宽带可变增益放大器(VGA)。作为设备的信号输出接口电路,VGA承担了输出信号放大、共模电压调节、驱动负载等重要功能,在很大程度上决定了设备的综合性能。设计了一款适用于宽带AWG的VGA芯片,采用一种改进的数字增益调节架构,在兼顾带宽的同时,消除了模拟控制电压的影响,并确保了增益的单调性。芯片采用SiGe BiCMOS工艺实现,测试结果表明,芯片可以实现0.125~2倍的单调增益控制,最小增益步进约为0.125倍;在输入信号频率为4 GHz时的输出信号衰减为-2.83 d B。

高精度可变增益放大器的研究与设计

为了实现可变增益放大器高精度及大动态范围的优势,基于GaAs 0.25μm pHEMT工艺,设计了一款工作在0.1~4.0 GHz并行控制的可变增益放大器。放大器由数控衰减器和射频放大器组成。数控衰减单元采用桥T型结构和电平转换电路来实现;正压控制衰减电路简化了电路结构,提高电路可靠性;改进型并联电容补偿衰减结构改善大衰减态高频衰减精度;射频放大器电路采用并联电阻负反馈的共源共栅(Cascode)结构,实现了高增益平坦度和大动态范围。测试结果显示,在工作频带内,可变增益放大器的增益可达20 dB以上、平坦度在1.5 dB以内,可变增益范围为0~31.5 dB、衰减步进0.5 dB,输出三阶交调点最高可达39 dBm,端口回波损耗均小于-15 dB。

一款3~6.3 GHz增益可调的低噪声放大器设计

针对无线接收机在对不同信号进行放大时,噪声恶化严重的问题,文中在驱动放大级采用电流复用技术,可以降低系统功耗,同时,在增益变化过程中保证了输入级增益对后级电路噪声的抑制作用,使得增益变化过程中,噪声始终低于1 dB。输入级和输出级阻抗匹配良好,在3 GHz~6.3 GHz的工作频段上可实现系统增益的连续可调范围约30 dB(19.6 dB~49.6 dB),同时通过采用两个控制电压分别控制两级放大电路,在增益变化过程中系统获得了良好的增益平坦度,版图尺寸为0.95×1.53 mm^(2)。在常规工作状态下,系统噪声为0.56±0.02 dB,增益为49.6±0.47 dB,功耗97 mW。在4.5 GHz频率处,系统的OP1dB为10.3 dBm,OIP3达到29 dBm,具有良好的线性度。

A CMOS variable gain LNA for UWB receivers

A CMOS variable gain low noise amplifier （LNA） is presented for 4.24.8 GHz ultra-wideband appli- cation in accordance with Chinese standard. The design method for the wideband input matching is presented and the low noise performance of the LNA is illustrated. A three-bit digital programmable gain control circuit is exploited to achieve variable gain. The design was implemented in 0.13μm RF CMOS process, and the die occupies an area of 0.9 mm2 with ESD pads. Totally the circuit draws 18 mA DC current from 1.2 V DC supply, the LNA exhibits minimum noise figure of 2.3 dB, S（1, 1） less than -9 dB and S（2, 2） less than -10 dB. The maximum and the minimum power gains are 28.5 dB and 16 dB respectively. The tuning step of the gain is about 4 dB with four steps in all. Also the input 1 dB compression point is -10 dBm and input third order intercept point （IIP3） is -2 dBm.

周期信号波形识别及参数测量装置的设计实现

设计使用STM32F407 MCU为核心,增加外围信号调理电路与程控可变增益放大器模块,实现了无需手动切换档位的周期信号的波形类型识别及频率、峰峰值、占空比测量功能。所设计系统能够测量50 mV≤Vpp≤10 V、1 Hz≤f≤50 kHz的正弦波、三角波、方波信号,并能够测量方波信号20%~80%的占空比。

A 3.8 GHz programmable gain amplifier with a 0.1 dB gain step

A broadband programmable gain amplifier（PGA） with a small gain step and low gain error has been designed in 0.13 m CMOS technology. The PGA was implemented with open-loop architecture to provide wide bandwidth. A two-stage gain control method, which consists of a resistor ladder attenuator and an active fine gain control stage, provides the small gain step. A look-up table based gain control method is introduced in the fine gain control stage to lower the gain error.The proposedPGAshows a decibel-linear variable gainfrom4 to20 dB with a gain step of 0.1 dB and a gain error less than˙0.05 dB. The 3-dB bandwidth and maximum IIP3 are 3.8 GHz and 17 dBm, respectively.

可变增益放大器的实现方法

从应用的角度出发 ,给出了典型的可变增益放大器的实现方法 ,总结了实现方法的特点 。

CMOS可变增益放大器设计概述

可变增益放大器是模拟单元电路之一,起着变化增益、调整信号动态范围、稳定信号功率的作用。文章综述了CMOS集成可变增益放大器的研究情况;给出了可变增益放大器的定义、应用、分类和主要指标,描述了多种开环和闭环放大器的结构,分析了相应的增益控制方法及其优缺点;说明了在CMOS工艺下实现放大器增益按指数变化的几种途径。最后,介绍了用于无线数字通信,具有宽带、高线性、低电源电压等高性能可变增益放大器的设计实例。

中低频宽动态范围AGC放大器设计

自动增益控制(AGC)放大电路被广泛应用于各种音视频传输及数字中频接收系统中。介绍了一种基于AD603的快速AGC实现方法,详细分析了两级级联AD603的增益平衡分配方式,包括电路的压控检波,以及AGC起控点、输出幅度、总增益的调整方式,尤其是在低频段的改进方法。文中对其级间耦合的方式进行分析测试,实际测试其在40mV^7.5V输入时能稳定在800mV输出,低频至2kHz,且其输出幅度、增益范围以及各部分参数调整极为方便。

全捷联激光制导寻的器测角精度分析与优化

为了降低激光制导武器系统成本并保证打击精度,设计了全捷联激光制导寻的器,并对影响打击精度的关键技术指标测角精度进行了研究。首先对影响测角精度的主要因素增益控制进行了分析,通过对四通道可变增益放大器进行增益标定和最小二乘拟合得到增益控制曲线,接着讨论了离散量控制下增益补偿的方法及误差,仿真计算得到不同配置模式下增益补偿前和补偿后的光斑重心计算误差。对全捷联激光制导寻的器进行激光照射测角试验,结果表明,增益补偿后能够消除系统误差约5.6 mrad,在中心线性视场范围内,测角精度达到2 mrad。该系统满足某机载轻型空地导弹对激光制导寻的器测角精度的要求,为精确末制导提供保障。

一种3～5GHz连续增益可调CMOS超宽带LNA的设计

提出了一种具有大范围连续增益变化的3～5GHzCMOS可调增益低噪声放大器。采用两级共源共栅电路结构，二阶切比雪夫滤波器作为输入，源跟随器作为输出，在带内获得了良好的输入输出匹配和噪声性能。通过控制第二级的偏置电流，获得了36dB的连续增益可调，同时也不影响输入输出匹配。该电路基于TSMC0．18脚CMOS工艺，在最高增益时，输入和输出反射系数511和52z分别小于-10．1dB和-15dB，最高增益达到23．8dB，最小噪声系数仅为1．5dB，三阶交调截点为-7dBm，在1．2V电压下，功耗为6．8mW；芯片面积0．71mm^2（0．96mm×0．74mm）。

一种利用衰减器实现的超宽带可变增益放大器

提出了一种基于有源可调衰减器的超宽带可变增益放大器,以有源可调衰减器作为可变增益放大器的核心,并与高增益放大器级联,在3.1～10.6GHz超宽频带内实现了宽动态增益调节范围。基于Jazz 0.35μm SiGe HBT工艺,完成了超宽带可变增益放大器的设计,利用安捷伦公司的ADS仿真软件进行仿真验证。结果表明,在3.1～10.6GHz的超宽频带内,当电压在0.7～2.0V的范围内变化时,该放大器的动态增益变化范围大于60dB,3dB带宽大于7GHz,在整个电压变化范围内,S11和S22均低于-10dB,在最大增益处,噪声系数小于5dB。