Most of multimedia schemes employ variable-length codes (VLCs) like Huffman code as core components in obtaining high compression rates. However VLC methods are very sensitive to channel noise. The goal of this paper ...Most of multimedia schemes employ variable-length codes (VLCs) like Huffman code as core components in obtaining high compression rates. However VLC methods are very sensitive to channel noise. The goal of this paper is to salvage as many data from the damaged packets as possible for higher audiovisual quality. This paper proposes an integrated joint source-channel decoder (I-JSCD) at a symbol-level using three-dimensional (3-D) trellis representation for first-order Markov sources encoded with VLC source code and convolutional channel code. This method combines source code and channel code state-spaces and bit-lengths to construct a two-dimensional (2-D) state-space,and then develops a 3-D trellis and a maximum a-posterior (MAP) algorithm to estimate the source sequence symbol by symbol. Experiment results demonstrate that our method results in significant improvement in decoding performance,it can salvage at least half of (50%) data in any channel error rate,and can provide additional error resilience to VLC stream like image,audio,video stream over high error rate links.展开更多
Reversible variable length codes (RVLCs) have received much attention due to their excellent error resilient capabilities. In this paper, a novel construction algorithm for symmetrical RVLC is proposed which is indepe...Reversible variable length codes (RVLCs) have received much attention due to their excellent error resilient capabilities. In this paper, a novel construction algorithm for symmetrical RVLC is proposed which is independent of the Huffman code. The proposed algorithm's codeword assignment is only based on symbol occurrence probability. It has many advantages over symmetrical construction algorithms available for easy realization and better code performance. In addition, the proposed algorithm simplifies the codeword selection mechanism dramatically.展开更多
A novel Variable-Length Code (VLC), called Alternate VLC (AVLC), is proposed in this letter, which employs two types of VLC to encode source symbols alternately. Its advantage is that it can not only stop the symbol e...A novel Variable-Length Code (VLC), called Alternate VLC (AVLC), is proposed in this letter, which employs two types of VLC to encode source symbols alternately. Its advantage is that it can not only stop the symbol error propagation effect, but also correct symbol insertion errors and avoid symbol deletion er-rors, so the original sequence number of symbols can be kept correctly, which is very important in video com-munication.展开更多
A novel Joint Source and Channel Decoding (JSCD) scheme for Variable Length Codes (VLCs) concatenated with turbo codes utilizing a new super-trellis decoding algorithm is presented in this letter. The basic idea of ou...A novel Joint Source and Channel Decoding (JSCD) scheme for Variable Length Codes (VLCs) concatenated with turbo codes utilizing a new super-trellis decoding algorithm is presented in this letter. The basic idea of our decoding algorithm is that source a priori information with the form of bit transition probabilities corresponding to the VLC tree can be derived directly from sub-state transitions in new composite-state represented super-trellis. A Maximum Likelihood (ML) decoding algorithm for VLC sequence estimations based on the proposed super-trellis is also described. Simu-lation results show that the new iterative decoding scheme can obtain obvious encoding gain especially for Reversible Variable Length Codes (RVLCs),when compared with the classical separated turbo decoding and the previous joint decoding not considering source statistical characteristics.展开更多
This paper presents an efficient VLSI architecture of the contest-based adaptive variable length code (CAVLC) decoder with power optimized for the H.264/advanced video coding (AVC) standard. In the proposed design, ac...This paper presents an efficient VLSI architecture of the contest-based adaptive variable length code (CAVLC) decoder with power optimized for the H.264/advanced video coding (AVC) standard. In the proposed design, according to the regularity of the codewords, the first one detector is used to solve the low efficiency and high power dissipation problem within the traditional method of table-searching. Considering the relevance of the data used in the process of runbefore’s decoding, arithmetic operation is combined with finite state machine (FSM), which achieves higher decoding efficiency. According to the CAVLC decoding flow, clock gating is employed in the module level and the register level respectively, which reduces 43% of the overall dynamic power dissipation. The proposed design can decode every syntax element in one clock cycle. When the proposed design is synthesized at the clock constraint of 100 MHz, the synthesis result shows that the design costs 11 300 gates under a 0.25 μm CMOS technology, which meets the demand of real time decoding in the H.264/AVC standard.展开更多
In this paper, we present a Joint Source-Channel Decoding algorithm (JSCD) for Low-Density Parity Check (LDPC) codes by modifying the Sum-Product Algorithm (SPA) to account for the source redun-dancy, which results fr...In this paper, we present a Joint Source-Channel Decoding algorithm (JSCD) for Low-Density Parity Check (LDPC) codes by modifying the Sum-Product Algorithm (SPA) to account for the source redun-dancy, which results from the neighbouring Huffman coded bits. Simulations demonstrate that in the presence of source redundancy, the proposed algorithm gives better performance than the Separate Source and Channel Decoding algorithm (SSCD).展开更多
This paper proposes an efficient H.264/AVC entropy decoder.It requires no ROM/RAM fabrication process that decreases fabrication cost and increases operation speed.It was achieved by optimizing lookup tables and inter...This paper proposes an efficient H.264/AVC entropy decoder.It requires no ROM/RAM fabrication process that decreases fabrication cost and increases operation speed.It was achieved by optimizing lookup tables and internal buffers,which significantly improves area,speed,and power.The proposed entropy decoder does not exploit embedded processor for bitstream manipulation, which also improves area,speed,and power.Its gate counts and maximum operation frequency are 77515 gates and 175MHz in 0.18um fabrication process,respectively.The proposed entropy decoder needs 2303 cycles in average for one macroblock decoding.It can run at 28MHz to meet the real-time processing requirement for CIF format video decoding on mobile applications.展开更多
基金Supported by the Foundation of Ministry of Education of China (211CERS10)
文摘Most of multimedia schemes employ variable-length codes (VLCs) like Huffman code as core components in obtaining high compression rates. However VLC methods are very sensitive to channel noise. The goal of this paper is to salvage as many data from the damaged packets as possible for higher audiovisual quality. This paper proposes an integrated joint source-channel decoder (I-JSCD) at a symbol-level using three-dimensional (3-D) trellis representation for first-order Markov sources encoded with VLC source code and convolutional channel code. This method combines source code and channel code state-spaces and bit-lengths to construct a two-dimensional (2-D) state-space,and then develops a 3-D trellis and a maximum a-posterior (MAP) algorithm to estimate the source sequence symbol by symbol. Experiment results demonstrate that our method results in significant improvement in decoding performance,it can salvage at least half of (50%) data in any channel error rate,and can provide additional error resilience to VLC stream like image,audio,video stream over high error rate links.
基金Project (No. 60172030) partially supported by the National Natural Science Foundation of China
文摘Reversible variable length codes (RVLCs) have received much attention due to their excellent error resilient capabilities. In this paper, a novel construction algorithm for symmetrical RVLC is proposed which is independent of the Huffman code. The proposed algorithm's codeword assignment is only based on symbol occurrence probability. It has many advantages over symmetrical construction algorithms available for easy realization and better code performance. In addition, the proposed algorithm simplifies the codeword selection mechanism dramatically.
文摘A novel Variable-Length Code (VLC), called Alternate VLC (AVLC), is proposed in this letter, which employs two types of VLC to encode source symbols alternately. Its advantage is that it can not only stop the symbol error propagation effect, but also correct symbol insertion errors and avoid symbol deletion er-rors, so the original sequence number of symbols can be kept correctly, which is very important in video com-munication.
基金Supported by the National Natural Science Foundation of China (No.90304003, No.60573112, No.60272056)the Foundation Project of China (No.A1320061262).
文摘A novel Joint Source and Channel Decoding (JSCD) scheme for Variable Length Codes (VLCs) concatenated with turbo codes utilizing a new super-trellis decoding algorithm is presented in this letter. The basic idea of our decoding algorithm is that source a priori information with the form of bit transition probabilities corresponding to the VLC tree can be derived directly from sub-state transitions in new composite-state represented super-trellis. A Maximum Likelihood (ML) decoding algorithm for VLC sequence estimations based on the proposed super-trellis is also described. Simu-lation results show that the new iterative decoding scheme can obtain obvious encoding gain especially for Reversible Variable Length Codes (RVLCs),when compared with the classical separated turbo decoding and the previous joint decoding not considering source statistical characteristics.
基金Project supported by the Applied Materials Shanghai Research and Development Foundation (Grant No.08700741000)the Foundation of Shanghai Municipal Education Commission (Grant No.2006AZ068)
文摘This paper presents an efficient VLSI architecture of the contest-based adaptive variable length code (CAVLC) decoder with power optimized for the H.264/advanced video coding (AVC) standard. In the proposed design, according to the regularity of the codewords, the first one detector is used to solve the low efficiency and high power dissipation problem within the traditional method of table-searching. Considering the relevance of the data used in the process of runbefore’s decoding, arithmetic operation is combined with finite state machine (FSM), which achieves higher decoding efficiency. According to the CAVLC decoding flow, clock gating is employed in the module level and the register level respectively, which reduces 43% of the overall dynamic power dissipation. The proposed design can decode every syntax element in one clock cycle. When the proposed design is synthesized at the clock constraint of 100 MHz, the synthesis result shows that the design costs 11 300 gates under a 0.25 μm CMOS technology, which meets the demand of real time decoding in the H.264/AVC standard.
文摘In this paper, we present a Joint Source-Channel Decoding algorithm (JSCD) for Low-Density Parity Check (LDPC) codes by modifying the Sum-Product Algorithm (SPA) to account for the source redun-dancy, which results from the neighbouring Huffman coded bits. Simulations demonstrate that in the presence of source redundancy, the proposed algorithm gives better performance than the Separate Source and Channel Decoding algorithm (SSCD).
基金sponsored by ETRI System Semiconductor Industry Promotion Center,Human Resource Development Project for SoC Convergence.
文摘This paper proposes an efficient H.264/AVC entropy decoder.It requires no ROM/RAM fabrication process that decreases fabrication cost and increases operation speed.It was achieved by optimizing lookup tables and internal buffers,which significantly improves area,speed,and power.The proposed entropy decoder does not exploit embedded processor for bitstream manipulation, which also improves area,speed,and power.Its gate counts and maximum operation frequency are 77515 gates and 175MHz in 0.18um fabrication process,respectively.The proposed entropy decoder needs 2303 cycles in average for one macroblock decoding.It can run at 28MHz to meet the real-time processing requirement for CIF format video decoding on mobile applications.
