CMOS Realization of VDVTA and OTA Based Fully Electronically Tunable First Order All Pass Filter with Optimum Linearity at Low Supply Voltage ±0.85 V

This paper presents a new first order all pass filter configurations. The proposed all pass filter configuration employs two configurations namely VDVTA and OTAs based first order all pass filter configuration. The first proposed configuration employs a single VDVTA and one grounded capacitor whereas the second proposed configuration employs two OTAs and one grounded capacitor. Both types of proposed configurations are fully electronically tunable and their quality factors do not depend on tunable pole frequency range. The reported configurations yield low active and passive sensitivities and also have low power consumption with very low supply voltage ± 0.85 V with Bias Voltage ± 0.50 V. The PSPICE simulation of the proposed VDVTA and two OTAs based first order all pass filter configurations are verified using 0.18 μm CMOS Technology Process Parameters.

Systematic Synthesis of Compressive VDTA-Based T-T Filter with Orthogonal Control of f_o and Q

Based on sixteen nullor-mirror models of the voltage differencing transconductance amplifier (VDTA) and port admittance matrices of the tow-Thomas (T-T) filter with orthogonal control between the characteristic frequency(f_0) and figure of merit (Q),two different categories of the voltage-mode and transconductance-mode T-T filters are synthesized by the means of the nodal admittance matrix (NAM) expansion method.The category A filter that employs two compressive VDTAs and two grounded capacitors includes four structures,and the category B filter that uses two compressive VDTAs,two grounded capacitors,and one grounded resistor,also includes four structures.These circuits are suitable for integrated circuit manufacture,and their parameters f_0 and Q can be orthogonally adjusted with varying the bias currents of VDTAs.After the paper and pencil test is completed,the computer analyses,including alternating current (AC),parameter sweep,Monte Carlo (MC),and noise analyses,are performed to support the synthesis approach.

New VD-DIBA-Based Single-Resistance-Controlled Sinusoidal Oscillator

A new Single-Resistance-Controlled (SRC) sinusoidal oscillator using single Voltage Differencing-Differential Input Buffered Amplifier (VD-DIBA), only four passive components (two capacitors and two resistors), is presented. The proposed structure provides the following advantageous features: 1) independent control of oscillation frequency and condition of oscillation and 2) low active and passive sensitivities. The effects of non-idealities of the VD-DIBA on the proposed oscillator have also been investigated. The proposed SRC sinusoidal oscillator has been checked for robustness using Monte-Carlo simulation. SPICE simulation results have been included using 0.35 μm MIETEC technology to confirm the validity of the proposed SRC sinusoidal oscillator.

Cache Memory Design for Single Bit Architecture with Different Sense Amplifiers

Most modern microprocessors have one or two levels of on-chip caches to make things run faster,but this is not always the case.Most of the time,these caches are made of static random access memory cells.They take up a lot of space on the chip and use a lot of electricity.A lot of the time,low power is more important than several aspects.This is true for phones and tablets.Cache memory design for single bit architecture consists of six transistors static random access memory cell,a circuit of write driver,and sense amplifiers(such as voltage differential sense amplifier,current differential sense amplifier,charge transfer differential sense amplifier,voltage latch sense amplifier,and current latch sense amplifier,all of which are compared on different resistance values in terms of a number of transistors,delay in sensing and consumption of power.The conclusion arises that single bit six transistor static random access memory cell voltage differential sense amplifier architecture consumes 11.34μW of power which shows that power is reduced up to 83%,77.75%reduction in the case of the current differential sense amplifier,39.62%in case of charge transfer differential sense amplifier and 50%in case of voltage latch sense amplifier when compared to existing latch sense amplifier architecture.Furthermore,power reduction techniques are applied over different blocks of cache memory architecture to optimize energy.The single-bit six transistors static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique consumes 8.078μW of power,i.e.,reduce 28%more power that makes single bit six transistor static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique more energy efficient.

A low-voltage sense amplifier with two-stage operational amplifier clamping for flash memory

A low-voltage sense amplifier with reference current generator utilizing two-stage operational amplifier clamp structure for flash memory is presented in this paper,capable of operating with minimum supply voltage at1 V.A new reference current generation circuit composed of a reference cell and a two-stage operational amplifier clamping the drain pole of the reference cell is used to generate the reference current,which avoids the threshold limitation caused by current mirror transistor in the traditional sense amplifier.A novel reference voltage generation circuit using dummy bit-line structure without pull-down current is also adopted,which not only improves the sense window enhancing read precision but also saves power consumption.The sense amplifier was implemented in a flash realized in 90 run flash technology.Experimental results show the access time is 14.7 ns with power supply of 1.2 V and slow corner at 125℃.

Synthesis for Current-Mode Sallen-Key Filter Using VDTAs

In this work, an original Sallen-Key second-order low-pass filter is first turned into a current-mode one by means of the adjoint network theorem. Two nodal admittance matrices(NAM) of the filter are then educed. Furthermore, these two matrices are expanded through NAM expansion approach, generating one current-mode Sallen-Key filter, which uses two compact voltage differential trans-conductance amplifiers(VDTAs) and two grounded capacitors, implements not only one low-pass transfer function but two band-pass transfer functions, and provides the non-interrelated control between the natural frequency and quality factor. As an example of the synthesized filter, a second-order VDTA filter with fo=1 MHz, Q=1, HLP=-HBP1=HBP2=1 is designed. The used synthesis approach has been confirmed with the help of circuit and computer analysis.