MoS2/Zr composite films were deposited on the cemented carbide YT14 （WC＋14%TiC＋6%Co） by medium-frequency magnetron sputtered and coupled with multi-arc ion plated techniques.The influence of negative bias voltage ...MoS2/Zr composite films were deposited on the cemented carbide YT14 （WC＋14%TiC＋6%Co） by medium-frequency magnetron sputtered and coupled with multi-arc ion plated techniques.The influence of negative bias voltage on the composite film properties,including adhesion strength,micro-hardness,thickness and tribological properties were investigated.The results showed that proper negative bias voltage could significantly improve the mechanical and tribological properties of composite films.The effects of negative bias voltage on film properties were also put forward.The optimal negative bias voltage was -200 V under this experiment conditions.The obtained composite films were dense,the adhesion strength was about 60 N,the thickness was about 2.4 μm,and the micro-hardness was about 9.0 GPa.The friction coefficient and wear rate was 0.12 and 2.1×10-7 cm3/N·m respectively after 60 m sliding operation against hardened steel under a load of 20 N and a sliding speed of 200 rev·min-1.展开更多
A 680 V LDMOS on a thin SOI with an improved field oxide（FOX） and dual field plate was studied experimentally.The FOX structure was formed by an ＂oxidation-etch-oxidation＂ process,which took much less time to form...A 680 V LDMOS on a thin SOI with an improved field oxide（FOX） and dual field plate was studied experimentally.The FOX structure was formed by an ＂oxidation-etch-oxidation＂ process,which took much less time to form,and had a low protrusion profile.A polysilicon field plate extended to the FOX and a long metal field plate was used to improve the specific on-resistance.An optimized drift region implant for linear-gradient doping was adopted to achieve a uniform lateral electric field.Using a SimBond SOI wafer with a 1.5μm top silicon and a 3μm buried oxide layer,CMOS compatible SOI LDMOS processes are designed and implemented successfully. The off-state breakdown voltage reached 680 V,and the specific on-resistance was 8.2Ω·mm^2.展开更多
基金Funded by the National Natural Science Foundation of China (No.51075237)the National Basic Research Program of China (No.2009CB724402)+3 种基金the Taishan Scholar Program of Shandong Provincethe Outstanding Young Scholar Science Foundation of Shandong (No.JQ200917)the National Natural Science Foundation of Shandong (No.ZR2010EZ002)National High Technology Research and Development Program (No.2009AA044303)
文摘MoS2/Zr composite films were deposited on the cemented carbide YT14 （WC＋14%TiC＋6%Co） by medium-frequency magnetron sputtered and coupled with multi-arc ion plated techniques.The influence of negative bias voltage on the composite film properties,including adhesion strength,micro-hardness,thickness and tribological properties were investigated.The results showed that proper negative bias voltage could significantly improve the mechanical and tribological properties of composite films.The effects of negative bias voltage on film properties were also put forward.The optimal negative bias voltage was -200 V under this experiment conditions.The obtained composite films were dense,the adhesion strength was about 60 N,the thickness was about 2.4 μm,and the micro-hardness was about 9.0 GPa.The friction coefficient and wear rate was 0.12 and 2.1×10-7 cm3/N·m respectively after 60 m sliding operation against hardened steel under a load of 20 N and a sliding speed of 200 rev·min-1.
基金Project supported by the National Natural Science Foundation of China(Nos.11175229,61006088)
文摘A 680 V LDMOS on a thin SOI with an improved field oxide（FOX） and dual field plate was studied experimentally.The FOX structure was formed by an ＂oxidation-etch-oxidation＂ process,which took much less time to form,and had a low protrusion profile.A polysilicon field plate extended to the FOX and a long metal field plate was used to improve the specific on-resistance.An optimized drift region implant for linear-gradient doping was adopted to achieve a uniform lateral electric field.Using a SimBond SOI wafer with a 1.5μm top silicon and a 3μm buried oxide layer,CMOS compatible SOI LDMOS processes are designed and implemented successfully. The off-state breakdown voltage reached 680 V,and the specific on-resistance was 8.2Ω·mm^2.
