Power Synchronization Compensation Strategy Based on Second-order Compensation Links for Voltage-controlled Inverters in Microgrids

A second-order compensation link is adopted to control voltage-controlled inverters(VCIs) in microgrid systems to enhance the performance of the power synchronization process of the inverter. The second-order compensation link is classified as both a real pole compensator(RPC) and a complex pole compensator(CPC) according to the pole position. Given a model for the VCI power output, the design process for the second-order compensation link, which is equipped with an RPC and a CPC, is detailed. Moreover, the frequency-domain compensation effects of the RPC and CPC are analyzed using the root locus and Bode diagrams of the system before and after compensation. Finally, the compensation effects of the two types of second-order compensators are compared with the commonly used high-pass filter using MATLAB/Simulink, which verifies the RPC and CPC strategies. Simulation results show that the two types of compensators designed in this study can effectively increase the system cutting frequency and improve the phase margin in the frequency domain while accelerating the power synchronization process, simultaneously making it smoother and reducing overshoot in the time domain. The RPC has better gain robustness, whereas the CPC has better time constant robustness. By implementing an RPC or a CPC, the dynamic time of the power synchronization compensation strategy is reduced within 0.5 s, and the overshoot is reduced within 10% in the experiments with two inverters.

Improved Fractional-order Damping Method for Voltage-controlled DFIG System Under Weak Grid

When a doubly-fed induction generator(DFIG)is connected to a weak grid,the coupling between the grid and the DFIG itself will increase,which will cause stability problems.It is difficult to maintain the tracking accuracy and robustness of the phase-locked loop(PLL)in the weak grid,and the risk of instability of the current-controlled DFIG(CC-DFIG)system will increase.In this paper,a new type of voltage-controlled DFIG(VC-DFIG)mode is adopted,which is a grid-forming structure that can independently support the voltage and frequency with a certain adaptability in the weak grid.A small-signal impedance model of the VC-DFIG system is also established.The impedance of DFIG inevitably generates coupling with the grid impedance in the weak grid,especially in parallel compensation grids,and results in resonance.On the basis of the VC-DFIG,impedance stability analysis is performed to study the influences of the control structure and short-circuit ratio.Then,a feedforward damping method is proposed to modify the impedance of the VC-DFIG system at resonance frequencies.The proposed fractional order damping is utilized,which can enhance the robustness and rapidity of resonance suppression under parameter fluctuations.Finally,the experimental results are presented to validate the effectiveness of the proposed control strategy.

A Survey of Voltage-Controlled-Oscillator-Based ?∑ ADCs

The benefits of technology scaling have fueled interest in realizing time-domain oversampling(?∑) of Analog-to-Digital Converters(ADCs). Voltage-Controlled Oscillators(VCO) are increasingly used to design ?∑ADCs because of their simplicity, high digitization, and low-voltage tolerance, making them a promising candidate to replace the classical Operational Transconductance Amplifier(OTA) in ?∑ ADC design. This work aims to provide a summary of the fully VCO-based ?∑ ADCs that are highly digital and scaling-friendly. This work presents a review of first-order and high-order VCO-based ?∑ ADCs with several techniques and architectures to mitigate the nonidealities introduced by VCO, achieving outstanding power efficiency. The contributions and drawbacks of these techniques and architectures are also discussed.

High voltage-controlled magnetic anisotropy and interface magnetoelectric effect in sputtered multilayers annealed at high temperatures

Voltage control of magnetism promises great energy efficiency in writing magnetic memory. Here, using Cr/Mo/CoFeB/MgO multilayers stable under high annealing temperatures up to 590°C, we significantly enhance the interfacial crystallinity, thereby the interface-originated perpendicular magnetic anisotropy(PMA), voltage-controlled magnetic anisotropy(VCMA), and interface magnetoelectric(ME) effect. High interfacial PMA of 1.35 mJ/m^2, VCMA coefficient of-138 fJ/(V m), and interface ME coefficient, which is 2-3 orders of magnitude larger than ab initio calculation results are simultaneously achieved after annealing at 500°C. These promising results enabled by the industry-applicable sputtering process will pave the way for highdensity voltage-controlled spintronic devices.

A micromechanical bridge-shaped voltage-controlled oscillator

A novel micromechanical bridge-shaped voltage-controlled oscillator with high Q value was fabricated. The core of this kind of oscillators is an electrothermally excited and piezoresistively detected micromechanical bridge resonator. Its resonance frequency can be adjusted by changing the DC voltage applied to the Wheatstone bridge. Theoretical analysis and experimental data show that its resonance frequency is linear with the square of the DC voltage. The linearity is better than 0.16% and the adjustable frequency range excels 17.15%.

Voltage-controlled transmission through a dielectric slab doped with quantum dot molecules

Transmission and reflection of an electromagnetic pulse through a dielectric slab doped with the quantum dot molecules are investigated. It is shown that the transmission and reflection coefficients depend on the inter-dot tunneling effect and can be simply controlled by applying a gate voltage without any changing in the refractive index or thickness of the slab. Such simple controlling prepares an active beam splitter which can be used in all optical switching, optical limiting, and other optical systems.

Gate-voltage control of alternating-current-driven skyrmion propagation in ferromagnetic nanotrack devices

Magnetic skyrmions, with topologically protected particle-like magnetization configurations, are promising information carriers for future spintronics devices with ultralow energy consumption. Generally, during motion, skyrmions suffer from the skyrmion Hall effect(Sk HE) wherein the skyrmions deflect away from the intended path of the driving force.Numerous methods have been proposed to avoid this detrimental effect. In this study, we propose controllable alternating current(AC)-driven skyrmion propagation in a ferromagnetic nanowire based on combination of gate-voltage-controlled magnetic anisotropy(VCMA) and Sk HE. Micromagnetic simulations show that a skyrmion oscillatory closed-loop-like in situ motion driven by AC can be transformed into directional ratchet-like propagation along the nanotrack by creating a VCMA-gate barrier. Additionally, we show that the skyrmion propagation conditions depend on the gate barrier potential and driving AC parameters, and they can be used for the optimal design of nanotrack devices. Moreover, this mechanism could be used to control skyrmion macroscopic propagation directions by dynamically alternating the voltage of another series of gates. We further show the dynamic control of the long-distance propagation of skyrmions along with the pinning state. The study results provide a promising route for designing future skyrmion-based spintronics logical and memory devices.

Charge-mediated voltage modulation of magnetism in Hf_(0.5)Zr_(0.5)O_(2)/Co multiferroic heterojunction

We construct the Hall-bar device with the size of several hundred nanometers based on the HZO/Co multiferroic heterojunction. A remarkable voltage-controlled magnetism is observed in the device that possesses both ferroelectric property and perpendicular magnetic anisotropy(PMA). The nucleation field and coercivity can be modulated by voltage pulse while saturation field keeps stable. The non-volatile and reversible voltage-controlled magnetism is ascribable to interfacial charges caused by ferroelectric polarization. Meanwhile, the effective anisotropy energy density(Ku) can also be controlled by voltage pulse, a decrease of 83% and increase of 28% in Kuare realized under-3-V and 3-V pulses,respectively. Because the energy barrier is directly proportional to Ku under a given volume, a decreased or enhanced energy barrier can be controlled by voltage pulse. Thus, it is an effective method to realize low-power and high-stability magneto-resistive random-access memory(MRAM).

Dual-Delay-Path Ring Oscillator with Self-Biased Delay Cells for Clock Generation

This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structurebased clock generation and digital system driving. For a voltage supply VDD = 1.8 V, the resulting set of performance parameters include power consumption PDC = 4.68 mW and phase noise PN@1MHz = -107.8 dBc/Hz. From the trade-off involving PDC and PN, a system level high performance is obtained considering a reference figure-of-merit ( FoM = -224 dBc/Hz ). Implemented at schematic level by applying CMOS-based technology (UMC L180), the proposed VCRO was designed at Cadence environment and optimized at MunEDA WiCkeD tool.

A Large Dynamic Range Floating Memristor Emulator With Equal Port Current Restriction

In this paper, a large dynamic range floating memristor emulator(LDRFME) with equal port current restriction is proposed to be achieved by a large dynamic range floating voltage-controlled linear resistor(VCLR). Since real memristors have not been largely commercialized until now, the application of a LDRFME to memristive systems is reasonable. Motivated by this need, this paper proposes an achievement of a LDRFME based on a feasible transistor model. A first circuit extends the voltage range of the triode region of an ordinary junction field effect transistor(JFET). The idea is to use this JFET transistor as a tunable linear resistor. A second memristive non-linear circuit is used to drive the resistance of the first JFET transistor. Then those two circuits are connected together and, under certain conditions, the obtained "resistor" presents a hysteretic behavior,which is considered as a memristive effect. The electrical characteristics of a LDRFME are validated by software simulation and real measurement, respectively.

A Configuration for Realizing Voltage Controlled Floating Inductance and Its Application

A configuration using current feedback amplifiers AD844 and multiplier AD534 has been presented, which is capable of realizing Voltage Controlled Floating Inductance (proportional and in-verse proportional). The application of band pass filter in Figure 4(a), notch filter in Figure 5(a) and Hartley oscillator in Figure 6(a) and simulation result in Figures 4(b)-(d), Figures 5(b)-(d), Figures 6(b)-(d) shows the workability of proposed configuration.

Low Phase Noise and Wide Tuning Range VCO Using the MOS Differential Amplifier with Active Load

We demonstrate the design of a novel voltage-controlled oscillator (VCO), which is based on a metal-oxide-semiconductor field-effect transistor (MOS) differential amplifier with active load. This VCO achieves low phase noise and wide tuning range. The phase noise is –120 dBc/Hz at 600 KHz offset from a 1.216 GHz carrier frequency. This value is comparable to that of a LC-based integrated oscillator. The operating frequency can be tuned from 117 MHz to 1.216 GHz with the supply voltage varying from 1.3 V to 3.3 V. Therefore, the tuning range is about 90.38% which is larger than most of the LC and ring oscillator. The VCO circuit, which is constructed using a standard 0.35 μm CMOS technology, occupies only 26.25 × 7.52 μm2 die area and dissipated 10.56 mW under a 3.3 V supply voltage.

Chip design of a 5.8-GHz fractional-N frequency synthesizer with a tunable G_m-C loop filter

This paper proposes a novel Gm-C loop filter instead of a conventional passive loop filter used in a phase-locked loop. The innovative advantage of the proposed architecture is tunable loop filter bandwidth and hence the process variations of passive elements of resistance R and capacitance C can be overcome and the chip area is greatly reduced. Furthermore, the MASH 1-1-1 sigma-delta （ZA） modulator is adopted for performing the fractional division number and hence improves the phase noise as well. Measured results show that the locked phase noise is -114.1 dBc/Hz with lower Gm-C bandwidth and -111.7 dBm/C with higher Gm-C bandwidth at 1 MHz offset from carrier of 5.68 GHz. Including pads and built-in Gm-C filter, the chip area of the proposed frequency synthesizer is 1.06 mm2. The output power is -8.69 dBm at 5.68 CHz and consumes 56 mW with an off-chip buffer from 1.8-V supply voltage.

A Simple On-Chip Automatic Tuning Circuit for Continuous-Time Filter

A simple on-chip automatic frequency tuning circuit is proposed. The tuning circuit is modified from voltage-controlled filter (VCF) frequency tuning circuit. We utilize an operational transconductance amplifier and a capacitor to from a single-time constant (STC) circuit which can produce a controllable delay time clock to tune the frequency of the filter. It can efficiently reduce the deviations in the 3 dB bandwidth from the variations of PVT (Process, Voltage and Temperature). The design of the STC circuit is simpler than VCF and it has less chip area. The chip has been implanted using TCMC 0.35 μm CMOS technology and the power consumption is less than 9.05 mW.

Switchable PLL Frequency Synthesizer andHot Carrier Effects

In this paper, a new strategy of switchable CMOS phase-locked loop frequency synthesizer is proposed to increase its tuning range. The switchable PLL which integrates two phase-locked loops with different tuning frequencies are designed and fabricated in 0.5 μm n-well CMOS process. Cadence/Spectre simulations show that the frequency range of the switchable phased-locked loop is between 320 MHz to 1.15 GHz. The experimental results show that the RMS jitter of the phase-locked loop changes from 26 ps to 123 ps as output frequency varies. For 700 MHz carrier frequency, the phase noise of the phase-locked loop reaches as low as ?81 dBc/Hz at 10 kHz offset frequency and ?104 dBc/Hz at 1 MHz offset frequency. A device degradation model due to hot carrier effects has been used to analyze the jitter and phase noise performance in an open loop voltage-controlled oscillator. The oscillation frequency of the voltage-controlled oscillator decreases by approximately 100 to 200 MHz versus the bias voltage and the RMS jitter increases by 40 ps under different phase-locked loop output frequencies after 4 hours of stress time.

Two Simple Analog Multiplier Based Linear VCOs Using a Single Current Feedback Op-Amp

Two simple voltage-controlled-oscillators (VCO) with linear tuning laws employing only a single current feedback operational amplifier (CFOA) in conjunction with two analog multipliers (AM) have been highlighted. The workability of the presented VCOs has been demonstrated by experimental results based upon AD844 type CFOAs and AD534 type AMs.

New Integrators and Differentiators Using a MMCC

Using the new building block Multiplication-Mode Current Conveyor (MMCC), some inverting/non-inverting type integrator and differentiator designs are presented, wherein the time constant (τ) is tuned electronically. The MMCC is implemented by a readily available chip-level configuration using a multiplier (ICL 8013) and a current feedback amplifier (AD-844 IC) CFA. Detailed analysis, taking into account the device non-idealities, had been carried out that indicates slight deviations affecting the values of the nominal time constant but the design is practically insensitive to the port mismatch errors (ε). Satisfactory response on wave conversion, for signal frequencies up to 600 Khz had been verified with both hardware circuit test and PSPICE macromodel simulation.

An Electrically Scanned Lens Antenna for 2-D Scanning

An electrically scanned lens antenna for two dimensional scanning is presented. The antenna system is composed of a (N × 1) feed array, a binary diffractive dielectric lens (BDL) and a voltage-controlled ferroelectric lens (VCFL). The feeds at different offset foci of the BDL generate receiving beams pointing to different angles to perform beam scanning in one dimension;the VCFL made of ferroelectric slabs which show linear permittivity gradient when loaded with corresponding DC voltages generate linear phase shift to steer the beam in the other dimension.

NBTI Impact on RF Front End in Wireless Sensor Networks

In wireless sensor network （WSN）, the communication node is the heart of the whole system. Negative bias temperature instability （NBTI） is becoming one of the most important factors that decide the life time of node chips, especially with the feature size declining. In this paper, the NBTI impact on the front-end circuits in the WSN nodes is studied, such as voltage-controlled oscillator （VCO）, charge pump （CP）, low noise amplifier （LNA）, and even the whole transceiver system. The circuit level NBTI degeneration models are built for the key modules and the entire transceiver. It is shown that the phase noise of the VCO will be deteriorated, the current mismatch of the CP and the noise figure of the LNA will both be increased, and the sensitivity and the adjacent channel selectivity （ACS） will be depressed by NBTI. The conclusions are proved by simulation results using HJTC 0.18 μm technology.

A low power wide-band CMOS PLL frequency synthesizer for portable hybrid GNSS receiver

The design consideration and implementation of a CMOS frequency synthesizer for the portable hybrid global navigation satellite system are presented. The large tuning range is achieved by tuning curve compensation using an improved VCO resonant tank, which reduces the power consumption and obtains better phase noise performance. The circuit is validated by simulations and fabricated in a standard 0.18 μm 1P6M CMOS process. Close-loop phase noise measured is lower than -95 dBc at 200 kHz offset while the measured ttming range is 21.5% from 1.47 to 1.83 GHz. The proposed synthesizer including source coupled logic prescaler consumes 6.2 mA current from 1.8 V supply. The whole silicon required is only 0.53 mm2.