2.5Gb/s Monolithic IC of Clock Recovery,Data Decision,and 1∶4 Demultiplexer

A high integrated monolithic IC, with functions of clock recovery, data decision, and 1 ： 4 demultiplexer,is implemented in 0.25μm CMOS process for 2.5Gb/s fiber-optic communications. The recovered and frequency divided 625MHz clock has a phase noise of -106.26dBc/Hz at 100kHz offset in response to a 2.5Gb/s PRBS input data （2^31-1）. The 2.5Gb/s PRBS data are demultiplexed to four 625Mb/s data. The 0.97mm× 0.97mm IC consumes 550mW under a single 3.3V power supply （not including output buffers）.

20Gb/s 1∶2 Demultiplexer in 0.18μm CMOS

A 1 ：2 demultiplexer is designed and realized in standard 0. 18μm CMOS technology. A novel high-speed and low-voltage latch is used to realize the core circuit cell. Compared to the traditional source-coupled FET logic structure latch, its power supply voltage is lower and the speed is faster. In addition, the negative feedback is used in the buffer circuit to widen its bandwidth. Measurement results show that the chip can work at the data rate of 20Gb/ s. The supply voltage is 1.8V and the current,including the buffer circuit, is 72mA.

A kind of low-power 10 Gbit/s CMOS 1∶4 demultiplexer

A 10 Gbit/s 1：4 demultiplexer（DEMUX） fabricated in 0. 18 μm CMOS （complementary metal-oxidesemiconductor transistor） technology for optical-fiber-link is presented. The system is constructed in tree-type structure and it includes a high-speed 1 ： 2 DEMUX, two low-speed 1 ： 2 DEMUXs, a divider, and input and output buffers for data and dock. To improve the circuit performance and reduce the power consumption, a latch structure with a common-gate topology and a single clock phase is employed in the high-speed 1 ： 2 DEMUX and the 5 GHz 1 ： 2 on-chip frequency divider, while dynamic CMOS logic is adopted in the low-speed l ： 2 DEMUXs. Measured results at 10 Gbit/s by 23^31 -1 pseudo random bit sequences （PRBS） via on-wafer testing indicate that it can work well with a power dissipation of less than 100 mW at 1.8 V supply voltage. The die area of the DEMUX is 0. 65 mm × 0. 75 mm.

12Gb/s 0.25μm CMOS Low-Power 1∶4 Demultiplexer

A low power 12Gb/s single-stage 1 ： 4 demultiplexer （DEMUX） applied in SONET OC-192 is realized in TSMC＇s mix-signal 0. 25μm CMOS. All of the circuits are in source coupled FET logic （SCFL） to achieve as high a speed as possible and suppress common mode distortions. This DEMUX is featured for achieving singlestage demultiplexing by using a quarter-rate IQ clock. This method not only reduces the components of the DEMUX but also lowers its power dissipation. The fabricated DEMUX operates error free at 12Gb/s by 231 - 1 pseudorandom bit sequences in on-wafer testing. The chip size is 0. 9mm × 0.9mm and the power dissipation is only 210mW with a single 2.5V supply.

20 Gbit/s 1∶2 demultiplexer of low-power using 0.18 μm CMOS

A 1 ： 2 demultiplexer（DEMUX） that is fabricated using 0. 18 μm CMOS （complementary metaloxide-semiconductor transistor） technology is presented. The DEMUX consists of a master-slave-slave, masterslave D flip-flops and output buffers. The D flip-flop employs a dynamic-loading structure and common-gate topology with single clock phase for the bias transistors. The dynamic-loading structure can make the circuit work faster because it decreases the charge/discharge time of the output node, and it consumes lower power because its working current is in a switch mode. In addition, the positive feedback loop, which is made up of a cross-coupled transistor pair in the latch, speeds up the circuit. Measurement results at 20 Gbit/s 2^23 - 1 pseudo random bit sequence （PRBS） via on-wafer testing show that the 1： 2 DEMUX can operate well. The power dissipation is 108 mW with the area of 475μm×578μm.

10 Gbit/s 0.25μm CMOS 1∶4 demultiplexer

A 10 Gbit/s (STM-64, OC-192) 1:4 demultiplexer (DEMUX) with 4-phase clock wasachieved in TSMC's standard 0.25 μm complementary metal-oxide-semiconductor (CMOS) technique. Allof the circuits are in source coupled FET logic (SCFL) to achieve as high as possible speed andsuppress common mode distortions. This DEMUX is featured by constant-delay buffers to generate a4-phase clock and adjust skews of the four channel outputs. The fabricated DEMUX operates error freeat 10 Gbit/s by 2^(31) -1 pseudorandom bit sequences (PRBS) via on-wafer testing. The measured rootmean square (rms) jitter, rising and failing edge of the eye-diagram are 11, 123 and 137 ps,respectively. The chip size is 0.9 mm x 1.2 mm and the power dissipation is 550 mW with a 3. 3 Vsupply.

Semi-vectorial analysis of a compact wavelength demultiplexer based on the tapered multimode interference coupler

Based on a parabolically tapered multimode interference （MMI） coupler with a deep-etched SiO2/SiON rib waveguide, a compact wavelength demultiplexer operating at 1.30 and 1.55 μm wavelengths is proposed and analysed by using three-dimensional semi-vectorial finite-difference beam propagation method （3D-SV-FD-BPM）. The results show that a MMI section of 330.0 μm in length, which is only 76% length of a straight MMI coupler, is achieved with the contrasts of 42.3 and 39.2dB in quasi-TE mode, and 38.4 and 37.8dB in quasi-TM mode at wavelengths 1.30 and 1.55μm, respectively, and the insertion losses below 0.2dB at both wavelengths and in both polarization states, The alternating direction implicit algorithm with the Crank-Nicholson scheme is applied to the discretization of the 3D-SV-FD-BPM formulation along the longitudinal direction. Moreover, a modified FD scheme is constructed to approximate the resulting equations along the transverse directions, in which the discontinuities of the derivatives of magnetic field components Hy and Hx along the vertical and horizontal interfaces, respectively, are involved.

Designing thermal demultiplexer: Splitting phonons by negative mass and genetic algorithm optimization

We propose the concept of thermal demultiplexer, which can split the heat flux in different frequency ranges intodifferent directions. We demonstrate this device concept in a honeycomb lattice with dangling atoms. From the view ofeffective negative mass, we give a qualitative explanation of how the dangling atoms change the original transport property.We first design a two-mass configuration thermal demultiplexer, and find that the heat flux can flow into different ports incorresponding frequency ranges roughly. Then, to improve the performance, we choose the suitable masses of danglingatoms and optimize the four-mass configuration with genetic algorithm. Finally, we give out the optimal configuration witha remarkable effect. Our study finds a way to selectively split spectrum-resolved heat to different ports as phonon splitter,which would provide a new means to manipulate phonons and heat, and to guide the design of phononic thermal devices inthe future.

High-performance and fabrication friendly polarization demultiplexer

A compact and fabrication friendly polarization demultiplexer(P-DEMUX) is proposed and characterized to enable wavelength-division-multiplexing and polarization-division-multiplexing simultaneously. The proposed structure is composed of a polarization-selective microring resonator in ultrathin waveguide and two bus channels in the silicon nitridesilica-silicon horizontal slot waveguides. In the slot waveguide, the transverse electric(TE) mode propagates through the silicon layer, while the transverse magnetic(TM) mode is confined in the slot region. In the designed ultra-thin waveguide, the TM mode is cut-off. The effective indexes of the TE modes for ultrathin and slot waveguides have comparable values. Thanks for these distinguishing features, the input TE mode can be efficiently filtered through the ultra-thin microring at the resonant wavelength, while the TM mode can directly output from the through port. Simulation results show that the extinction ratio of the proposed P-DEMUX for TE and TM modes are 33.21 dB and 24.97 dB, and the insertion losses are 0.346 dB and 0.324 dB, respectively, at the wavelength of 1551.64 nm. Furthermore, the device shows a broad bandwidth(> 100 nm) for an extinction ratio(ER) of > 20 dB. In addition, the proposed P-DEMUX also has a good fabrication tolerance for the waveguide width variation of-20 nm≤ △w_(g)≤ 20 nm and the microring width variation of -20 nm≤ △w_(r) ≤20 nm for a low insertion loss of < 0.75 dB and low ER of <-18 dB.

Erratum to“Designing thermal demultiplexer:Splitting phonons by negative mass and genetic algorithm optimization”

Equations(8)and(9)in the original paper[Chin.Phys.B 30036301(2021)]are corrected.

Bound in continuum states and induced transparency in mesoscopic demultiplexer with two outputs

We investigate the electronic transport in a simple mesoscopic cross structure made of two wires(stubs)grafted at the same point along a quantum waveguide.We show that the structure may exhibit important phenomena such as bound in continuum(BIC)states.These states are transformed into electromagnetically induced transparency(EIT)resonance by detuning slightly the lengths of the stubs.The last phenomenon is used to propose and study a mesoscopic demultiplexer device with an input waveguide and two output waveguides.We give closed-form expressions of the geometrical parameters that allow a selective transfer of a given state in the first waveguide without perturbing the second waveguide.The effect of temperature on the transmission resonances is also examined by using Landauer-Büttiker formula.The analytical results of the dispersion relation and transmission and reflection coefficient are obtained using the Green's function method.

All-Optical 3:8 Decoder with the Help of Terahertz Optical Asymmetric Demultiplexer

An all-optical 3:8 decoder unit with the help of terahertz optical asymmetric demultiplexer (TOAD) is proposed. The all-optical 3:8 decoder unit with a set of all-optical full-adders and optical exclusive-ORs (XORs), can be used to perform a fast central processor unit using optical hardware components. We try to exploit the advantages of TOAD-based optical switch to design an integrated all-optical circuit which can perform decoding of signal. A theoretical model is presented and verified through numerical simulation. The new method promises both higher processing speed and accuracy. The model can be extended for studying more complex all-optical circuit of enhanced functionality in which decoder is the basic building block. The operation of the proposed circuit is parallel in nature. The impact of the switching energy with small signal gain and variation of extinction ratio and contrast ration with control pulse energy of the switching outcome is explored and assessed by means of numerical simulations.

Optical Arithmetic Operation Using Optical Demultiplexer

Using Terahertz Optical Asymmetric Demultiplexer (TOAD) based switch we have designed all-optical parallel half adder and full adder. The approach to design this all-optical arithmetic circuit not only enhances the computational speed but also is capable of synthesizing light as input to produce desire output. The main advantage of parallel circuit is synchronization of input which is not required. All the circuits are designed theoretically and verified through numerical simulations.

Design of 2-to-4 All-Optical Decoder with the Help of Terahertz Optical Asymmetric Demultiplexer

An all-optical 2-to-4 decoder unit with the assist of terahertz optical asymmetric demultiplexer (TOAD) is presented. The all-optical 2-to-4 decoder with a set of all-optical switches is designed which can be used to achieve a high-speed central processor unit using optical hardware. The unique output lines can be used for all-optical header processing. We attempt to develop an integrated all-optical circuit which can perform decoding of signal. This scheme is very simple and flexible for performing different logic operation and to design advanced complex logic. Simulated results are confirming the described methods.

Designs of All-Optical Higher-Order Signed-Digit Adders Using Polarization-Encoded Based Terahertz-Optical-Asymmetric-Demultiplexer (TOAD)

Various designed circuits for multiple-valued all-optical arithmetic are demonstrated. The terahertz-optical-asymmetric-demultiplexer (TOAD) switch is used as the basic structure unit in the proposed circuits due to its compact size, thermal stability, and low power operation. The designs of trinary and quaternary signed-digit numbers based adders are presented using different polarized states of light. These proposed polarization-encoded based adders use much less switches and their speeds are higher than the intensity-encoded counterparts. Further, it will be shown that one of the proposed trinary signed-digit adders is twice as fast as a recently reported modified signed-digit adder.

用于光交换的硅基二氧化硅AWGR的设计与研究(特邀)

【目的】以N×N矩阵形式构成的阵列波导光栅路由器(AWGR)具有光学并行和波长路由能力,能在不同信道上同时传输N路信号,具有扩展性好、延时低和频带宽等优势,结合可调谐光源能实现快速光交换,是下一代光交换数据中心网络的潜在技术方案之一。为了解决现有AWGR在实际应用中存在的串扰大、有额外耦合损耗、偏振敏感和损耗非均匀性大等问题,进一步扩大数据中心规模和提升数据交换速度,文章分别对4×4和12×12通道的AWGR进行了研究。【方法】文章通过仿真软件进行基本设计参数的计算,分析研究了AWGR设计流程,并采用光束传播法(BPM)进行了仿真模拟。同时,采用在平板波导和条形波导连接处加入锥形波导taper结构和增大输入、输出波导间距等方法进行了性能优化。【结果】仿真结果得到良好的性能参数:4×4 AWGR插入损耗为-0.714 dB,串扰为-35.556 dB,损耗非均匀性为1.907 dB;12×12 AWGR插入损耗为-0.294 dB,串扰为-36.019 dB,损耗非均匀性为3.428 dB。文章制作设计器件流片并进行了性能测试,结果表明:4×4 AWGR插入损耗为-2.586 dB,串扰为-29.473 dB,损耗非均匀性为1.921 dB;12×12 AWGR插入损耗为-3.692 dB,串扰为-23.874 dB,损耗非均匀性为3.873 dB。【结论】文章的研究在串扰和损耗非均匀性等方面进行了性能优化,为后续设计迭代和进一步提升性能参数积累了经验。

On-chip terahertz orbital angular momentum demultiplexer

The terahertz regime is widely recognized as a fundamental domain with significant potential to address the demands of next-generation wireless communications.In parallel,mode division multiplexing based on orbital angular momentum(OAM)shows promise in enhancing bandwidth utilization,thereby expanding the overall communication channel capacity.In this study,we present both theoretical and experimental demonstrations of an on-chip terahertz OAM demultiplexer.This device effectively couples and steers seven incident terahertz vortex beams into distinct high-quality focusing surface plasmonic beams,and the focusing directions can be arbitrarily designated.The proposed design strategy integrates space-to-chip mode conversion,OAM recognition,and on-chip routing in a compact space with subwavelength thickness,exhibiting versatility and superior performance.

时分复用双光子成像系统高速数据处理研究

为满足高频脉冲时分复用的双独立扫描探测双光子显微成像系统中信号解多路复用、行场同步、像素值重建的需求,对高速数据的采集处理进行了研究;基于LabVIEW FPGA,结合有限状态机、FIFO缓存和并行流水线等技术,设计了一种多功能采集处理系统,通过精确的时序控制,成功实现了高速数据的无损解复用和后续成像数据处理,并能够对共振振镜非线性运动导致的图像畸变进行校正;经过调试仿真和实验测试表明,在系统单通道采样率800 MSPS、200 MHz FPGA处理时钟下,能够对160 MHz时间交错激光脉冲产生的来自不同位置的相应荧光信号进行复杂处理;经实际应用表明,系统满足实时成像的需求,为相关领域的研究者提供了有益的参考。

多通道片上微纳波分解复用器的智能逆设计

为获得超小超密集的波分解复用器,提出多通道片上微纳波分解复用器的智能逆设计方法,引入序列二次规划(SQP)算法和有限元法(FEM),辅以插值、整形和二值化等技术手段,实现从功能需求到具体结构的逆向设计。通过该方法,成功设计出多种类型的波分解复用器,并对它们进行实验验证。实验结果表明,所设计的波分解复用器在尺寸、传输效率和消光比等方面均表现出色。

磁带地震数据解编中的常见问题与解决方法

随着采集技术以及采集装备的发展,采集的地震数据格式及其磁带存储方式都发生了变化,导致地震数据处理系统经常无法正确解编磁带数据。本文对解编磁带时遇到的常见问题进行了总结,并给出了解决问题的相关方法。