An improved parallel weighted bit-flipping（PWBF） algorithm is presented. To accelerate the information exchanges between check nodes and variable nodes, the bit-flipping step and the check node updating step of the ...An improved parallel weighted bit-flipping（PWBF） algorithm is presented. To accelerate the information exchanges between check nodes and variable nodes, the bit-flipping step and the check node updating step of the original algorithm are parallelized. The simulation experiments demonstrate that the improved PWBF algorithm provides about 0. 1 to 0. 3 dB coding gain over the original PWBF algorithm. And the improved algorithm achieves a higher convergence rate. The choice of the threshold is also discussed, which is used to determine whether a bit should be flipped during each iteration. The appropriate threshold can ensure that most error bits be flipped, and keep the right ones untouched at the same time. The improvement is particularly effective for decoding quasi-cyclic low-density paritycheck（QC-LDPC） codes.展开更多
该文提出一种改进的低密度奇偶校验(Low Density Parity-Check,LDPC)码的加权比特翻转译码算法。该算法引入了变量节点的更新规则,对翻转函数的计算更加精确,同时能够有效弱化环路振荡引起的误码。仿真结果表明,与已有的基于幅度和的加...该文提出一种改进的低密度奇偶校验(Low Density Parity-Check,LDPC)码的加权比特翻转译码算法。该算法引入了变量节点的更新规则,对翻转函数的计算更加精确,同时能够有效弱化环路振荡引起的误码。仿真结果表明,与已有的基于幅度和的加权比特翻转译码算法(SMWBF)相比,在加性高斯白噪声信道下,该文算法在复杂度增加很小的情况下获得了误码率性能的有效提升。展开更多
大量仿真表明,基于幅度和的改进型加权比特翻转(modified sum of the magnitude based weighted bit flipping,MSMWBF)译码算法对于行重/列重较小的低密度奇偶校验(low density parity-check,LDPC)码而言,展现出巨大的性能优势,但对于行...大量仿真表明,基于幅度和的改进型加权比特翻转(modified sum of the magnitude based weighted bit flipping,MSMWBF)译码算法对于行重/列重较小的低密度奇偶校验(low density parity-check,LDPC)码而言,展现出巨大的性能优势,但对于行重/列重较大的基于有限域几何(finite-geometry,FG)的LDPC码,性能损失严重。首先对此现象进行理论分析。其次,引入附加的偏移项对MSMWBF算法的校验方程可靠度信息进行修正,提高了算法对行重/列重较大的LDPC码的译码性能。仿真结果表明,在加性高斯白噪声信道下,误比特率为10-5时,相比于MSMWBF算法,在适度增加实现复杂度的条件下,所提算法可获得约0.63dB的增益。展开更多
针对Euclidean Geometry(EG)-LDPC码码字的循环特性以及FWBF(fast weighted bit flipping)算法的算法结构设计高速LDPC译码器。具体实现方法如下:首先通过对RAM进行合理的划分,赋给不同的RAM相应的规则号和初始地址值保证数据的无冲突存...针对Euclidean Geometry(EG)-LDPC码码字的循环特性以及FWBF(fast weighted bit flipping)算法的算法结构设计高速LDPC译码器。具体实现方法如下:首先通过对RAM进行合理的划分,赋给不同的RAM相应的规则号和初始地址值保证数据的无冲突存取,然后通过向量化操作实现运算数据的高速存取。此外,校验式品质计算模块通过引入一种新型的树形搜索电路来降低该模块的功耗和延迟。最后,对EG255码采用5路并行模式,在Cyclone III EP3C120F780C7芯片上实现,信息吞吐量可达75.98Mbs,占用芯片逻辑资源不超过23%,RAM资源不超过4%。展开更多
基金The National High Technology Research and Development Program of China (863Program) ( No2009AA01Z235,2006AA01Z263)the Research Fund of the National Mobile Communications Research Laboratory of Southeast University(No2008A10)
文摘An improved parallel weighted bit-flipping（PWBF） algorithm is presented. To accelerate the information exchanges between check nodes and variable nodes, the bit-flipping step and the check node updating step of the original algorithm are parallelized. The simulation experiments demonstrate that the improved PWBF algorithm provides about 0. 1 to 0. 3 dB coding gain over the original PWBF algorithm. And the improved algorithm achieves a higher convergence rate. The choice of the threshold is also discussed, which is used to determine whether a bit should be flipped during each iteration. The appropriate threshold can ensure that most error bits be flipped, and keep the right ones untouched at the same time. The improvement is particularly effective for decoding quasi-cyclic low-density paritycheck（QC-LDPC） codes.
文摘该文提出一种改进的低密度奇偶校验(Low Density Parity-Check,LDPC)码的加权比特翻转译码算法。该算法引入了变量节点的更新规则,对翻转函数的计算更加精确,同时能够有效弱化环路振荡引起的误码。仿真结果表明,与已有的基于幅度和的加权比特翻转译码算法(SMWBF)相比,在加性高斯白噪声信道下,该文算法在复杂度增加很小的情况下获得了误码率性能的有效提升。
文摘大量仿真表明,基于幅度和的改进型加权比特翻转(modified sum of the magnitude based weighted bit flipping,MSMWBF)译码算法对于行重/列重较小的低密度奇偶校验(low density parity-check,LDPC)码而言,展现出巨大的性能优势,但对于行重/列重较大的基于有限域几何(finite-geometry,FG)的LDPC码,性能损失严重。首先对此现象进行理论分析。其次,引入附加的偏移项对MSMWBF算法的校验方程可靠度信息进行修正,提高了算法对行重/列重较大的LDPC码的译码性能。仿真结果表明,在加性高斯白噪声信道下,误比特率为10-5时,相比于MSMWBF算法,在适度增加实现复杂度的条件下,所提算法可获得约0.63dB的增益。
文摘针对Euclidean Geometry(EG)-LDPC码码字的循环特性以及FWBF(fast weighted bit flipping)算法的算法结构设计高速LDPC译码器。具体实现方法如下:首先通过对RAM进行合理的划分,赋给不同的RAM相应的规则号和初始地址值保证数据的无冲突存取,然后通过向量化操作实现运算数据的高速存取。此外,校验式品质计算模块通过引入一种新型的树形搜索电路来降低该模块的功耗和延迟。最后,对EG255码采用5路并行模式,在Cyclone III EP3C120F780C7芯片上实现,信息吞吐量可达75.98Mbs,占用芯片逻辑资源不超过23%,RAM资源不超过4%。
