To improve the full well capacity （FWC） of a small size backside illuminated （BSI） CMOS image sensor （CIS）, the effect of photodiode capacitance （Cpo） on FWC is studied, and a reformed pinned photodiode （PPD...To improve the full well capacity （FWC） of a small size backside illuminated （BSI） CMOS image sensor （CIS）, the effect of photodiode capacitance （Cpo） on FWC is studied, and a reformed pinned photodiode （PPD） structure is proposed. Two procedures are implemented for the optimization. The first is to form a varying doping concentration and depth stretched new N region, which is implemented by an additional higher-energy and lower-dose N type implant beneath the original N region. The FWC of this structure is increased by extending the side wall junctions in the substrate. Secondly, in order to help the enlarged well capacity achieve full depletion, two step P-type implants with different implant energies are introduced to form a P-type insertion region in the interior of the stretched N region. This vertical inserted P region guarantees that the proposed new PD structure achieves full depletion in the reset period. The simulation results show that the FWC can be improved from 1289e- to 6390e-, and this improvement does not sacrifice any image lag performance. Additionally, quantum efficiency （QE） is enhanced in the full wavelength range, especially 6.3% at 520 nm wavelength. This technique can not only be used in such BSI structures, but also adopted in an FSI pixel with any photodiode-type readout scheme.展开更多
To improve the full-well capacity and linear dynamic range of CMOS image sensor,a special finger-shaped pinned photodiode(PPD)is designed.In terms of process,the first N-type ion implantation of the PPD N buried layer...To improve the full-well capacity and linear dynamic range of CMOS image sensor,a special finger-shaped pinned photodiode(PPD)is designed.In terms of process,the first N-type ion implantation of the PPD N buried layer is extended under the transfer gate,thereby increasing the PPD capacitance.Based on TCAD simulation,the width and spacing of PPD were precisely adjusted.A high full-well capacity pixel design with a pixel size of 6×6μm^2 is realized based on the 0.18μm CMOS process.The simulation results indicate that the pixel with the above structure and process has a depletion depth of 2.8μm and a charge transfer efficiency of 100%.The measurement results of the test chip show that the full-well capacity can reach 68650 e–.Compared with the conventional structure,the proposed PPD structure can effectively improve the full well capacity of the pixel.展开更多
基金Project supported by the National Natural Science Foundation of China(Nos.61036004,60976030)
文摘To improve the full well capacity （FWC） of a small size backside illuminated （BSI） CMOS image sensor （CIS）, the effect of photodiode capacitance （Cpo） on FWC is studied, and a reformed pinned photodiode （PPD） structure is proposed. Two procedures are implemented for the optimization. The first is to form a varying doping concentration and depth stretched new N region, which is implemented by an additional higher-energy and lower-dose N type implant beneath the original N region. The FWC of this structure is increased by extending the side wall junctions in the substrate. Secondly, in order to help the enlarged well capacity achieve full depletion, two step P-type implants with different implant energies are introduced to form a P-type insertion region in the interior of the stretched N region. This vertical inserted P region guarantees that the proposed new PD structure achieves full depletion in the reset period. The simulation results show that the FWC can be improved from 1289e- to 6390e-, and this improvement does not sacrifice any image lag performance. Additionally, quantum efficiency （QE） is enhanced in the full wavelength range, especially 6.3% at 520 nm wavelength. This technique can not only be used in such BSI structures, but also adopted in an FSI pixel with any photodiode-type readout scheme.
基金supported by the Tianjin Key Laboratory of Imaging and Sensing Microelectronic Technology。
文摘To improve the full-well capacity and linear dynamic range of CMOS image sensor,a special finger-shaped pinned photodiode(PPD)is designed.In terms of process,the first N-type ion implantation of the PPD N buried layer is extended under the transfer gate,thereby increasing the PPD capacitance.Based on TCAD simulation,the width and spacing of PPD were precisely adjusted.A high full-well capacity pixel design with a pixel size of 6×6μm^2 is realized based on the 0.18μm CMOS process.The simulation results indicate that the pixel with the above structure and process has a depletion depth of 2.8μm and a charge transfer efficiency of 100%.The measurement results of the test chip show that the full-well capacity can reach 68650 e–.Compared with the conventional structure,the proposed PPD structure can effectively improve the full well capacity of the pixel.
