For wired local area networks(LANs),their effectiveness and invulnerability are very critical.It is extraordinarily significant to evaluate the network performance effectively in the design of a reasonable network top...For wired local area networks(LANs),their effectiveness and invulnerability are very critical.It is extraordinarily significant to evaluate the network performance effectively in the design of a reasonable network topology and the performance improvement of the networks.However,there are many factors affecting the performance of the networks,and the relation among them is also complicated.How to evaluate the performance of the wired LANs more accurately has been a heavy challenge in the network research.In order to solve the problem,this paper presents a performance evaluation method that evaluates the effectiveness and invulnerability of the wired LANs.Compared to traditional statistical methods,it has the distinct advantage of being able to handle several dependent variables simultaneously and tolerates the measurement errors among these independent variables and dependent variables.Finally,the rationality and validity of this method are verified by the extensive experimental simulation.展开更多
This paper describes a built-in self-test (BIST) hardware overheadminimization technique used during a BIST synthesis process. The technique inserts a minimal amountof BIST resources into a digital system to make it f...This paper describes a built-in self-test (BIST) hardware overheadminimization technique used during a BIST synthesis process. The technique inserts a minimal amountof BIST resources into a digital system to make it fully testable. The BIST resource insertion isguided by the results of symbolic testability analysis. It takes into consideration both BISTregister cost and wiring overhead in order to obtain the minimal area designs. A Simulated Annealingalgorithm is used to solve the overhead minimization problem. Experiments show that consideringwiring area during BIST synthesis results in smaller final designs as compared to the cases when thewiring impact is ignored.展开更多
基金supported by the National Natural Science Foundations of China (Nos.61572435,61472305, 61473222)the Ningbo Natural Science Foundations(Nos. 2016A610035,2017A610119)+1 种基金the Complex Electronic System Simulation Laboratory (No.DXZT-JC-ZZ-2015015)the Joint Fund of China State Shipbuilding Corporation(No.6141B03010103)
文摘For wired local area networks(LANs),their effectiveness and invulnerability are very critical.It is extraordinarily significant to evaluate the network performance effectively in the design of a reasonable network topology and the performance improvement of the networks.However,there are many factors affecting the performance of the networks,and the relation among them is also complicated.How to evaluate the performance of the wired LANs more accurately has been a heavy challenge in the network research.In order to solve the problem,this paper presents a performance evaluation method that evaluates the effectiveness and invulnerability of the wired LANs.Compared to traditional statistical methods,it has the distinct advantage of being able to handle several dependent variables simultaneously and tolerates the measurement errors among these independent variables and dependent variables.Finally,the rationality and validity of this method are verified by the extensive experimental simulation.
文摘This paper describes a built-in self-test (BIST) hardware overheadminimization technique used during a BIST synthesis process. The technique inserts a minimal amountof BIST resources into a digital system to make it fully testable. The BIST resource insertion isguided by the results of symbolic testability analysis. It takes into consideration both BISTregister cost and wiring overhead in order to obtain the minimal area designs. A Simulated Annealingalgorithm is used to solve the overhead minimization problem. Experiments show that consideringwiring area during BIST synthesis results in smaller final designs as compared to the cases when thewiring impact is ignored.
