A Worst-Case Execution Time Analysis Approach Based on Independent Paths for ARM Programs

To overcome disadvantages of traditional worst-case execution time （WCET） analysis approaches, we propose a new WCET analysis approach based on independent paths for ARM programs. Based on the results of program flow analysis, it reduces and partitions the control flow graph of the program and obtains a directed graph. Using linear combinations of independent paths of the directed graph, a set of feasible paths can be generated that gives complete coverage in terms of the program paths considered. Their timing measurements and execution counts of program segments are derived from a limited number of measurements of an instrumented version of the program. After the timing measurement of the feasible paths are linearly expressed by the execution times of program seg-ments, a system of equations is derived as a constraint problem, from which we can obtain the execution times of program segments. By assigning the execution times of program segments to weights of edges in the directed graph, the WCET estimate can be calculated on the basis of graph-theoretical techniques. Comparing our WCET estimate with the WCET measurement obtained by the exhaustive measurement, the maximum error ratio is only 8.259 3 %. It is shown that the proposed approach is an effective way to obtain the safe and tight WCET estimate for ARM programs.

Research on Multi-Core Processor Analysis for WCET Estimation

Real-time system timing analysis is crucial for estimating the worst-case execution time(WCET)of a program.To achieve this,static or dynamic analysis methods are used,along with targeted modeling of the actual hardware system.This literature review focuses on calculating WCET for multi-core processors,providing a survey of traditional methods used for static and dynamic analysis and highlighting the major challenges that arise from different program execution scenarios on multi-core platforms.This paper outlines the strengths and weaknesses of current methodologies and offers insights into prospective areas of research on multi-core analysis.By presenting a comprehensive analysis of the current state of research on multi-core processor analysis for WCET estimation,this review aims to serve as a valuable resource for researchers and practitioners in the field.

车控操作系统实时性/安全性保障技术

电子控制技术为智能网联汽车的高速发展持续赋能,车控操作系统是保障汽车电子控制软件安全、高效、实时运行的基石。随着智能网联汽车向集中式、端云融合式电子电气架构发展,车载硬件演化为多核异构处理器、弹性计算平台,车控软件向面向服务的软件架构转变,车控操作系统的架构、关键技术等也随之发展。综述了智能网联汽车用车控操作系统的发展历程与现状,对任务调度、实时性/安全性保障、形式化表征与验等基础理论和关键技术进行深入分析,阐述现有车控操作系统的技术挑战与发展趋势,为智能网联汽车的车控操作系统发展提供参考。

处理器时间侧信道攻防技术综述

现代处理器优化机制众多,设计人员在追求性能提升时,往往忽略背后的安全风险。时间侧信道攻击因其影响面广且隐蔽性好已成为最主要的安全威胁之一。随着瞬态执行攻击的出现,时间侧信道攻击的能力被进一步扩展,计算系统的安全基础被动摇。为此,处理器厂商及安全人员提出了大量防御机制。这些机制具有不同的防护能力及性能开销。与此同时,新的瞬态执行漏洞和隐蔽信道也不断被发现,已提出的防御机制被不断突破。围绕处理器时间侧信道攻防技术的博弈日益激烈。本文从基本攻击原理出发,对现有时间侧信道攻击进行了归纳总结,并在此基础上进一步分析了相关防御机制的保护能力和性能瓶颈,从而梳理出时间侧信道攻防技术的发展趋势,为未来软硬件系统开发和安全技术探索提供参考。

Timed SEFM:面向嵌入式实时控制系统的编程模型

实时任务的功能和其完成时间共同影响嵌入式控制系统的物理行为。传统的进程/线程模型缺乏时间语义,时间属性只能用优先级间接表达,任务的实际完成时间不具有确定性。Henzinger提出的LET(Logical Execution Time)编程模型用协作式的时间触发语义明确描述时间需求,但其所基于的操作系统仍沿用进程/线程模型,仍会引入时间不确定性。结合服务体/执行流模型SEFM(Servant/Exe-Flow Model)和LET模型,定义了一种时间确定的编程模型Timed SEFM,用改进的SEFM模型描述系统的功能行为,用LET描述系统的时间行为。把智能小车控制系统的实现作为研究实例。

基于查询编译的SQL执行技术研究进展

信息系统通常会借助数据管理系统来进行数据管理,其中SQL凭借良好的易用性和灵活性一直作为数据管理的主流查询语言,用户将编写的SQL语句交由数据管理系统执行后便可得到查询结果.执行模型的高效与否决定了系统能否快速响应用户的查询请求,现有执行模型主要采用解释执行和编译执行2种方式.解释执行具有良好的拓展性、可维护性等因而被大多数系统采用.不同于解释执行,编译执行为原本需要解释执行的查询生成高效的定制化代码来加速查询,带来的显著性能提升吸引了一众数据管理系统开始实现相应技术.然而,如何针对查询生成其对应的定制化代码是一个复杂的过程,在实现时需要考虑诸多方面,甚至在某些情况下,采用编译执行的查询性能可能还不及传统的火山模型.从概念、技术等角度系统地综述了编译执行技术的研究进展.首先,概述了编译执行的基本概念,对相关术语和背景知识进行了介绍;其次,分别从中间代码生成、中间表示、机器码生成与运行3个角度介绍了相关技术;最后,结合当前数据管理系统的研究趋势以及近期研究工作展望了编译执行未来的发展方向.

大规模云计算网络用户短时需求任务调度优化算法

设计一种大规模云计算网络用户短时需求任务调度优化算法,在较短的时间内处理大量的云计算任务,以满足用户短时需求。建立一个大规模云计算网络任务调度模型,将大规模云计算网络任务分配到各个虚拟机节点上,快速完成用户的短时需求任务;再通过遗传算法的个体编解码、自适应函数和遗传操作获取最优任务调度结果;并引入模拟退火算法,在遗传算法获取最佳调度结果的基础上进行局部搜索,直到迭代完成,输出最终的大规模云计算网络用户短时需求任务调度的全局最优解。实验结果表明:所设计算法能够实时关注用户任务执行状态以及用户任务执行时间;当用户任务数量为220时,该算法的单节点最大执行时间约为0.27 s,可提升整个任务调度的性能和效率;且该算法获取任务调度结果的收敛速度快、精度高。

机器人应用对企业内部薪酬差距的影响——基于多时点DID的实证

本文基于中国A股制造业上市公司数据,采用基于倾向得分匹配的多期双重差分法(PSM-DID)考察机器人应用对企业内部薪酬差距的影响及作用机制。结果发现,机器人应用能够显著缩小企业内部薪酬差距,在更换解释变量等一系列稳健性检验后结果依然稳健。机器人应用可通过促进企业创新及抑制盈余管理行为缩小企业内部薪酬差距,异质性检验结果表明机器人应用对企业内部薪酬差距的影响在规模更大、资本密集度更高的企业中更显著。进一步研究发现,机器人应用对企业内部薪酬差距的缩小显著表现为降低高管超额薪酬进而缩小企业内超额薪酬差距。本文研究为探索企业内部薪酬差距的治理机制提供了新视角,为我国在推动制造业转型升级的同时实现收入公平提供了重要参考。

基于PUF的TEE可信根生成方法研究

随着信息技术的快速发展,可信执行环境(TEE)在保障系统安全方面发挥着越来越重要的作用.然而,传统的TEE可信根生成方法存在诸多安全隐患,如易被复制、易遭受攻击等.因此,研究一种安全、可靠的可信根生成方法具有重要意义.针对现有TEE可信根生成方法的不足,提出了一种基于物理不可克隆函数(PUF)的TEE可信根生成方法.该方法利用PUF的唯一性和不可预测性,结合TEE的安全特性,生成具有唯一标识和高度安全性的可信根.为了验证所提方法的有效性,使用强PUF芯片和FPGA搭建了硬件验证平台,对所述方法进行了实验验证.实验结果表明,基于PUF的TEE可信根生成方法能够成功生成具有唯一性的可信根.

武钢铁路翻车机联系电路与全电子计算机联锁系统结合方案的研究

全电子计算机联锁系统是铁路信号控制领域的前沿技术。翻车机联系电路作为保障翻车机作业与铁路调车作业安全的重要设备,实现了车站推送作业、翻车机作业、溜放作业及车站其他运输作业之间互锁法。文章介绍了翻车机联系电路与全电子计算机联锁系统的结合方案。

芜湖单轨UTO全电子联锁系统技术特点

文章选择芜湖跨座式单轨全自动无人驾驶线路使用的EBILock950全电子计算机联锁系统作为研究对象,从该系统使用到的硬件架构原理、软件设计原理到全电子接口单元的典型配置分别展开阐述,同时也阐述了单轨道岔接口电路设计原理,全面展示了庞巴迪EBILock950全电子计算机联锁系统的主要技术特点,供业内人士了解单轨线路信号系统轨旁设计和全电子联锁应用技术参考。

The Dynamic Relationship of Brain Networks Across Time Windows During Product-Based Creative Thinking

Consensus of creativity research suggests that the measurement of both originality and valuableness is necessary when designing creativity tasks.However,few studies have emphasized valuableness when exploring underlying neural substrates of creative thinking.The present study employs product-based creativity tasks that measure both originality and valuableness in an exploration of the dynamic relationship between the default mode(DMN),executive control(ECN),and salience(SN)networks through time windows.This methodology highlights relevance,or valuableness,in creativity evaluation as opposed to divergent thinking tasks solely measuring originality.The researchers identified seven brain regions belonging to the ECN,DMN,and SN as regions of interest(ROIs),as well as four representative seeds to analyze functional connectivity in 25 college student participants.Results showed that all of the identified ROIs were involved during the creative task.The insula,precuneus,and ventrolateral prefrontal cortex(vlPFC)remained active across all stages of product-based creative thinking.Moreover,the connectivity analyses revealed varied interaction patterns of DMN,ECN,and SN at different thinking stages.The integrated findings of the whole brain,ROI,and connectivity analyses suggest a trend that the DMN and SN(which relate to bottom-up thinking)attenuate as time proceeds,whereas the vlPFC(which relates to top-down thinking)gets stronger at later stages;these findings reflect the nature of our creativity tasks and decision-making of valuableness in later stages.Based on brain region activation throughout execution of the task,we propose that product-based creative process may include three stages:exploration and association,incubation and insight,and finally,evaluation and decision making.This model provides a thinking frame for further research and classroom instruction.

品管圈应用于提高手术室Time out执行力的临床效果

目的:探讨品管圈活动对手术室Time out执行力的影响。方法:选择2019年1-4月笔者所在医院开展品管圈活动前收治的41例手术患者作为对照组,选择2019年7-10月笔者所在医院开展品管圈后收治的41例手术患者作为研究组。比较两组手术室Time out执行情况。结果:开展后手术室护士责任心、团队精神、沟通能力、解决问题能力评分均显著高于开展前,差异有统计学意义(P<0.05)。开展后手术室护士NPGA评分、CSES评分均显著高于开展前,差异有统计学意义(P<0.05)。研究组Time out执行内容准确率、填写准确率均显著高于对照组,差异有统计学意义(P<0.05)。结论:品管圈活动可改善手术室护士的核心自我评价及行为水平,提高其综合素质,有利于提高手术室Time out执行力,值得进一步推荐使用。

Employing Two ‘Sandwich Delay’ Mechanisms to Enhance Predictability of Embedded Systems Which Use Time-Triggered Co-Operative Architectures

In many real-time resource-constrained embedded systems, highly-predictable system behavior is a key design requirement. The “time-triggered co-operative” (TTC) scheduling algorithm provides a good match for a wide range of low-cost embedded applications. As a consequence of the resource, timing, and power constraints, the implementation of such algorithm is often far from trivial. Thus, basic implementation of TTC algorithm can result in excessive levels of task jitter which may jeopardize the predictability of many time-critical applications using this algorithm. This paper discusses the main sources of jitter in earlier TTC implementations and develops two alternative implementations – based on the employment of “sandwich delay” (SD) mechanisms – to reduce task jitter in TTC system significantly. In addition to jitter levels at task release times, we also assess the CPU, memory and power requirements involved in practical implementations of the proposed schedulers. The paper concludes that the TTC scheduler implementation using “multiple timer interrupt” (MTI) technique achieves better performance in terms of timing behavior and resource utilization as opposed to the other implementation which is based on a simple SD mechanism. Use of MTI technique is also found to provide a simple solution to “task overrun” problem which may degrade the performance of many TTC systems.

基于多级一致性协议的多核处理器WCET分析方法

由于多核处理器优越的计算性能,多核处理器现已广泛应用在嵌入式实时系统中.相对于单核处理器,多核处理器存在资源共享竞争、并行任务干扰等因素,尤其是缓存(Cache)一致性问题,导致任务最坏情况执行时间(worst-case execution time,WCET)的预测更加困难.基于以上因素,提出基于多级一致性协议的多核处理器WCET分析方法.该方法针对多级一致性协议体系架构,提出多级一致性域的概念,将多核处理器的数据访问分为域内访问和跨域访问2个层次,根据Cache读写策略和MESI(modify exclusive shared invalid)一致性协议,得出一致性域内部和跨一致性域的Cache状态更新函数,从而实现多级一致性协议嵌套情况下的WCET分析.实验结果表明,在改变Cache配置参数的情况下,该方法分析结果与GEM5仿真结果的变化趋势一致,经过相关性分析,GEM5仿真结果与该方法分析结果相关性系数不低于0.98;在分析精度方面,该方法的平均过估计率为1.30,相比现有方法降低了0.78.

A Requirements Engineering Environment for Embedded Real-Time Software—SREE

The paper presents the embedded real-time software-oriented requirements engineering environment—SREZ. It involves the whole process of software requirements engineering, including the definition, analysis and checking of requirements ,specifications. We first explain the principles of the executable specification language RTRSM. Subsequently, we introduce the main functions of SREE, illustrate the methods and techniques of checking requirements specifications, especially how to perform simulation execution, combining prototyping method with RTRSM and animated representations. At last, we compare the SREE with other requirements specifications methods and make a summary for SREE＇s advantages.

Time-Frequency Analysis of EEG Signals Evoked by Voluntary, Stimulated and Imaginary Motions

In order to investigate the characteristics of sensorimotor cortex during motor execution(ME), voluntary, stimulated and imaginary finger flexions were performed by ten volunteer subjects. Electroencephalogram(EEG) data were recorded according to the modified 10-20 International EEG System. The patterns were compared by the analysis of the motion-evoked EEG signals focusing on the contralateral(C3) and ipsilateral(C4) channels for hemispheric differences. The EEG energy distributions at alpha(8—13 Hz), beta(14—30 Hz) and gamma(30—50 Hz) bands were computed by wavelet transform(WT) and compared by the analysis of variance(ANOVA). The timefrequency(TF) analysis indicated that there existed a contralateral dominance of alpha post-movement event-related synchronization(ERS) pattern during the voluntary task, and that the energy of alpha band increased in the ipsilateral area during the stimulated(median nerve of wrist) task. Besides, the contralateral alpha and beta event-related desynchronization(ERD) patterns were observed in both stimulated and imaginary tasks. Another significant difference was found in the mean power values of gamma band(p<0.01)between the imaginary and other tasks. The results show that significant hemispheric differences such as alpha and beta band EEG energy distributions and TF changing phenomena(ERS/ERD) were found between C3 and C4 areas during all of the three patterns. The largest energy distribution was always at the alpha band for each task.

低年级农村儿童的视屏时间与执行功能的关系

随着农村儿童对电子产品使用频率的增多,电子产品的使用现状及其对认知能力的影响值得关注。通过问卷法,调查了426名小学一至三年级农村儿童电子产品使用情况与执行功能的水平,探讨视屏时间与执行功能这一高级认知能力之间的具体关系。结果发现,大多数低年级农村儿童每天使用电子产品娱乐和学习的视屏时间在1小时以下,无论平时还是周末,娱乐视屏时间都显著多于学习视屏时间;家长娱乐和学习的视屏时间与儿童的娱乐和学习视屏时间具有密切关系;儿童平时或周末的娱乐视屏时间与其执行功能之间呈负相关关系;在控制儿童使用电子产品娱乐的时间后,儿童平时或周末的学习视屏时间与其执行功能之间呈正相关关系。因此,如果要更好地发挥电子产品对儿童认知发展的积极影响,应合理控制儿童的娱乐视屏时间。