质子辐照作用下浮栅单元的数据翻转及错误退火

本文利用60 MeV质子束流,开展了NAND(not and)flash存储器的质子辐照实验,获取了浮栅单元的单粒子翻转截面,分析了浮栅单元错误的退火规律,研究了质子辐照对浮栅单元的数据保存能力的影响.实验结果表明,浮栅单元单粒子翻转截面随质子能量的升高而增大,随质子注量的升高而减小.浮栅单元错误随着退火时间的推移持续增多,该效应在低能量质子入射时更为明显.经质子辐照后,浮栅单元的数据保存能力有明显的退化.分析认为高能质子通过与靶原子的核反应,间接电离导致浮栅单元发生单粒子翻转,翻转截面与质子注量的相关性是因为浮栅单元单粒子敏感性的差异.质子引起的非电离损伤会在隧穿氧化层形成部分永久性的缺陷损伤,产生可以泄漏浮栅电子的多辅助陷阱导电通道,导致浮栅单元错误增多及数据保存能力退化.

A high-level synthesis based dual-module redundancy with multi-residue detection(DMR-MRD)fault-tolerant method for on-board processing satellite communication systems

On board processing(OBP) satellite systems have obtained more and more attentions in recent years because of their high efficiency and performance.However,the OBP transponders are very sensitive to the high energy particles in the space radiation environments.Single event upset(SEU)is one of the major radiation effects,which influences the satellite reliability greatly.Triple modular redundancy(TMR) is a classic and efficient method to mask SEUs.However,TMR uses three identical modules and a comparison logic,the circuit size becomes unacceptable,especially in the resource limited environments such as OBP systems.Considering that,a new SEU-tolerant method based on residue code and high-level synthesis(HLS) is proposed,and the new method is applied to FIR filters,which are typical structures in the OBP systems.The simulation results show that,for an applicable HLS scheduling scheme,area reduction can be reduced by 48.26%compared to TMR,while fault missing rate is 0.15%.

Efficient Single Event Upset-Tolerant FIR Filter Design Based on Residue Number for OBP Satellite Communication Systems

Cosmic radiation has several effects on the On-Board Processing(OBP)platform in satellite communications systems,and Single Event Upsets(SEUs)are one of its most important effects.In order to protect the Finite Impulse Response(FIR)filters against SEU,this paper proposes a novel Residue Number(RN)-based method.The proposed method applies the transpose form of the FIR filter to avoid the fault missing caused by SEU on shift registers.It also adjusts the input intelligently to avoid the fault missing caused by SEU on the filter coefficients.After all the fault missing events are avoided,the modulus can be minimised to achieve the minimum overhead.Theoretical analysis and simulation results show that the noise introduced by the input adjustment is negligible.Fault injection shows that the fault missing rate of the proposed method is zero.Finally,FPGA implementation shows that the overhead of the proposed method is approximately 75% of Triple Modular Redundancy,and is only 1%-2% higher than that of the traditional RN-based design.

Single event upset induced multi-block error and its mitigation strategy for SRAM-based FPGA

According to the SRAM-based FPGA's single event effect problem in space application,single event upset induced multi-block error(SEU-MBE) phenomenon and its mitigation strategy are studied in the paper.After analyzing the place and route result,the paper points out that the essence of SEU-MBE is that some important modules exceed the safe internal distance.Two approaches,area constraint method(ACM) and incremental route algorithm(IRA),are proposed,which can reduce the error rate by manipulating programmable switch matrix and interconnection points within FPGA route resource.Fault injection experiments indicate that error detection rate is above 98.6% for both strategies,and FPGA resources increment and performance penalty are around 10%.

A novel layout for single event upset mitigation in advanced CMOS SRAM cells

A novel layout has been proposed to reduce the single event upset(SEU) vulnerability of SRAM cells.Extensive 3-D technology computer-aided design(TCAD) simulation analyses show that the proposed layout can recover the upset-state much easier than conventional layout for larger space of PMOS transistors.For the angle incidence,the proposed layout is immune from ion hit in two plans,and is more robust against SEU in other two plans than the conventional one.The ability of anti-SEU is enhanced by at least 33% while the area cost reduced by 47%.Consequently,the layout strategy proposed can gain both reliability and area cost benefit simultaneously.

Simulation of the characteristics of low-energy proton induced single event upset

Monte Carlo simulation results are reported on the single event upset(SEU) triggered by the direct ionization effect of low-energy proton. The SEU cross-sections on the 45 nm static random access memory(SRAM) were compared with previous research work, which not only validated the simulation approach used herein, but also exposed the existence of saturated cross-section and the multiple bit upsets(MBUs) when the incident energy was less than 1 MeV. Additionally, it was observed that the saturated cross-section and MBUs are involved with energy loss and critical charge. The amount of deposited charge and the distribution with respect to the critical charge as the supplemental evidence are discussed.