[Objective] This study was to explore the growth characteristics and fruit quality of a new bud mutant line, ＇Chuanzao Loquat＇. [Method] Paraffin section technique combined with field investigation method were adopt...[Objective] This study was to explore the growth characteristics and fruit quality of a new bud mutant line, ＇Chuanzao Loquat＇. [Method] Paraffin section technique combined with field investigation method were adopted to conduct com- parative analysis of shoot histomorphology and phenological phases between two Io- quat varieties, ＇Chuanzao Loquat＇ and ＇Zaozhong 6＇. [Result] ＇Chuanzao Loquat＇ branched out and unfolded leaves about half to a month earlier than ＇Zaozhong 6＇; both the flowering and fruiting phases of ＇Chuanzao Loquat＇ were three months earlier than a precocious variety, ＇Zaozhong 6＇; the proportions of epidermis, cortex parenchyma, vascular tissue and medulla were 3.7%, 14.5%, 15.9% and 65.9%, re- spectively, in spdng shoots of ＇Chuanzao Loquat＇, and 3.1%, 42.5%, 6.9% and 47.5%, respectively, in ＇Zaozhong 6＇. [Conclusion] In terms of phenological phases, ＇Chuanzao Loqua＇ is earlier than ＇Zaozhong 6＇, a currently widely planted precocious variety, and thus is an important germplasm resource of Ioquats.展开更多
In the paper, related research and progress of molecular clock hypothesis were summarized, including definition of molecular clock, supporting proofs, contro- versy, significance and perfection, application and accomp...In the paper, related research and progress of molecular clock hypothesis were summarized, including definition of molecular clock, supporting proofs, contro- versy, significance and perfection, application and accompanying challenges.展开更多
A high integrated monolithic IC, with functions of clock recovery, data decision, and 1 ： 4 demultiplexer,is implemented in 0.25μm CMOS process for 2.5Gb/s fiber-optic communications. The recovered and frequency div...A high integrated monolithic IC, with functions of clock recovery, data decision, and 1 ： 4 demultiplexer,is implemented in 0.25μm CMOS process for 2.5Gb/s fiber-optic communications. The recovered and frequency divided 625MHz clock has a phase noise of -106.26dBc/Hz at 100kHz offset in response to a 2.5Gb/s PRBS input data （2^31-1）. The 2.5Gb/s PRBS data are demultiplexed to four 625Mb/s data. The 0.97mm× 0.97mm IC consumes 550mW under a single 3.3V power supply （not including output buffers）.展开更多
The design of a 2. 488 Gbit/s clock and data recovery （CDR） If for synchronous digital hierarchy （SDH） STM-16 receiver is described. Based on the injected phase-locked loop （IPLL） and D-flip flop architectures, ...The design of a 2. 488 Gbit/s clock and data recovery （CDR） If for synchronous digital hierarchy （SDH） STM-16 receiver is described. Based on the injected phase-locked loop （IPLL） and D-flip flop architectures, the CDR IC was implemented in a standard 0. 35 μan complementary metal-oxide-semiconductor （CMOS） technology. With 2^31 -1 pseudorandom bit sequences （PRBS） input, the sensitivity of data recovery circuit is less than 20 mV with 10^-12 bit error rate （BER）. The recovered clock shows a root mean square （rms） jitter of 2. 8 ps and a phase noise of - 110 dBc/Hz at 100 kHz offset. The capture range of the circuit is larger than 40 MHz. With a 5 V supply, the circuit consumes 680 mW and the chip area is 1.49 mm × 1 mm.展开更多
A 2.5Gb/s clock and data recovery （CDR） circuit is designed and realized in TSMC＇s standard 0.18/μm CMOS process. The clock recovery is based on a PLL. For phase noise optimization,a dynamic phase and frequency de...A 2.5Gb/s clock and data recovery （CDR） circuit is designed and realized in TSMC＇s standard 0.18/μm CMOS process. The clock recovery is based on a PLL. For phase noise optimization,a dynamic phase and frequency detector （PFD） is used in the PLL. The rms jitter of the recovered 2.5GHz clock is 2.4ps and the SSB phase noise is - 111dBc/Hz at 10kHz offset. The rms jitter of the recovered 2.5Gb/s data is 3.3ps. The power consumption is 120mW.展开更多
In this paper,a detailed analysis of a phase interpolator for clock recovery is presented. A mathematical model is setup for the phase interpolator and we perform a precise analysis using this model. The result shows ...In this paper,a detailed analysis of a phase interpolator for clock recovery is presented. A mathematical model is setup for the phase interpolator and we perform a precise analysis using this model. The result shows that the output amplitude and linearity of phase interpolator is primarily related to the difference between the two input phases. A new encoding pattern is given to solve this problem. Analysis in the circuit domain was also undertaken. The simulation results show that the relation between RC time-constant and time difference of input clocks affects the linearity of the phase interpolator. To alleviate this undesired effect, two adjustable-RC buffers are added at the input of the PI. Finally,a 90nm CMOS phase interpolator,which can work in the frequency from 1GHz to 5GHz,is proposed. The power dissipation of the phase interpolator is lmW with a 1.2V power supply. Experiment results show that the phase interpolator has a monotone output phase and good linearity.展开更多
A new low power quasi adiabatic logic,complementary pass transistor adiabatic logic (CPAL),is presented.The CPAL circuit is driven by a new three phase power clock,and its non adiabatic loss on output loads can b...A new low power quasi adiabatic logic,complementary pass transistor adiabatic logic (CPAL),is presented.The CPAL circuit is driven by a new three phase power clock,and its non adiabatic loss on output loads can be effectively reduced by using complementary pass transistor logic and transmission gates.Furthermore,the minimization of the energy consumption can be obtained by choosing the optimal size of bootstrapped nMOS transistors,thus it has more efficient energy transfer and recovery.A three phase power supply generator with a small control logic circuit and a single inductor is proposed.An 8 bit adder based on CPAL is designed and verified.With MOSIS 0 25μm CMOS technology,the CPAL adder consumes only 35% of the dissipated energy of a 2N 2N2P adder and is about 50% of the dissipated energy of a PFAL adder for clock rates ranging from 50 to 200MHz.展开更多
In order to make a 10 Gbit/s 2：1 half-rate multiplexer operate without external clocks, a 5 Gbit/s clock recovery （CR） circuit is needed to extract the desired clock from one input data. For the CR circuit, a 3-sta...In order to make a 10 Gbit/s 2：1 half-rate multiplexer operate without external clocks, a 5 Gbit/s clock recovery （CR） circuit is needed to extract the desired clock from one input data. For the CR circuit, a 3-stage ring voltage-controlled oscillator （VCO） is employed to avoid an unreliable startup of a 2-stage VCO and a low oscillation frequency of a 4-stage VCO. A phase frequency detector （PFD） is used to expand the pull-in range to meet the wide tuning range of a VCO required by process-voltage-temperature （PVT） variation. SMIC 0. 18-μm CMOS technology is adopted and the core area is 170 μm ×270 μm. Measurements show that, under a 1.8 V supply voltage, it consumes only about 90 mW, and has an input sensitivity of less than 25 mV, an output single-ended swing of above 300 mV, a phase noise of - 114 dBc/Hz at 1 MHz offset and a pull-in range of 1 GHz.展开更多
Based on the minimum settling time （MST） theory and step-response analysis of the second order system in active switched capacitor （SC） networks, a novel clock feedthrough frequency compensation （CFFC） method fo...Based on the minimum settling time （MST） theory and step-response analysis of the second order system in active switched capacitor （SC） networks, a novel clock feedthrough frequency compensation （CFFC） method for a folded-cascode OTA is proposed. The damping factor r/is adjusted by using MOS capacitors to introduce clock feedthrough so that the OTA can obtain the MST state and thus achieve fast settling. Research results indicate that the settling time of the compensated OTA is reduced by 22.7% ;as the capacitor load varies from 0.5 to 2.5pF,the improved settling time increases approximately linearly from 3.62 to 4.46ns： for VGA application, fast settling can also be achieved by modifying the MOS capacitor value accordingly when the closed loop gain of the compensated OTA varies.展开更多
文摘[Objective] This study was to explore the growth characteristics and fruit quality of a new bud mutant line, ＇Chuanzao Loquat＇. [Method] Paraffin section technique combined with field investigation method were adopted to conduct com- parative analysis of shoot histomorphology and phenological phases between two Io- quat varieties, ＇Chuanzao Loquat＇ and ＇Zaozhong 6＇. [Result] ＇Chuanzao Loquat＇ branched out and unfolded leaves about half to a month earlier than ＇Zaozhong 6＇; both the flowering and fruiting phases of ＇Chuanzao Loquat＇ were three months earlier than a precocious variety, ＇Zaozhong 6＇; the proportions of epidermis, cortex parenchyma, vascular tissue and medulla were 3.7%, 14.5%, 15.9% and 65.9%, re- spectively, in spdng shoots of ＇Chuanzao Loquat＇, and 3.1%, 42.5%, 6.9% and 47.5%, respectively, in ＇Zaozhong 6＇. [Conclusion] In terms of phenological phases, ＇Chuanzao Loqua＇ is earlier than ＇Zaozhong 6＇, a currently widely planted precocious variety, and thus is an important germplasm resource of Ioquats.
基金Supported by Hunan Education Reform ProjectEducation Reform Project of Hunan University of Humanities,Science and Technology(RKJGY1101)~~
文摘In the paper, related research and progress of molecular clock hypothesis were summarized, including definition of molecular clock, supporting proofs, contro- versy, significance and perfection, application and accompanying challenges.
文摘A high integrated monolithic IC, with functions of clock recovery, data decision, and 1 ： 4 demultiplexer,is implemented in 0.25μm CMOS process for 2.5Gb/s fiber-optic communications. The recovered and frequency divided 625MHz clock has a phase noise of -106.26dBc/Hz at 100kHz offset in response to a 2.5Gb/s PRBS input data （2^31-1）. The 2.5Gb/s PRBS data are demultiplexed to four 625Mb/s data. The 0.97mm× 0.97mm IC consumes 550mW under a single 3.3V power supply （not including output buffers）.
文摘The design of a 2. 488 Gbit/s clock and data recovery （CDR） If for synchronous digital hierarchy （SDH） STM-16 receiver is described. Based on the injected phase-locked loop （IPLL） and D-flip flop architectures, the CDR IC was implemented in a standard 0. 35 μan complementary metal-oxide-semiconductor （CMOS） technology. With 2^31 -1 pseudorandom bit sequences （PRBS） input, the sensitivity of data recovery circuit is less than 20 mV with 10^-12 bit error rate （BER）. The recovered clock shows a root mean square （rms） jitter of 2. 8 ps and a phase noise of - 110 dBc/Hz at 100 kHz offset. The capture range of the circuit is larger than 40 MHz. With a 5 V supply, the circuit consumes 680 mW and the chip area is 1.49 mm × 1 mm.
文摘A 2.5Gb/s clock and data recovery （CDR） circuit is designed and realized in TSMC＇s standard 0.18/μm CMOS process. The clock recovery is based on a PLL. For phase noise optimization,a dynamic phase and frequency detector （PFD） is used in the PLL. The rms jitter of the recovered 2.5GHz clock is 2.4ps and the SSB phase noise is - 111dBc/Hz at 10kHz offset. The rms jitter of the recovered 2.5Gb/s data is 3.3ps. The power consumption is 120mW.
文摘In this paper,a detailed analysis of a phase interpolator for clock recovery is presented. A mathematical model is setup for the phase interpolator and we perform a precise analysis using this model. The result shows that the output amplitude and linearity of phase interpolator is primarily related to the difference between the two input phases. A new encoding pattern is given to solve this problem. Analysis in the circuit domain was also undertaken. The simulation results show that the relation between RC time-constant and time difference of input clocks affects the linearity of the phase interpolator. To alleviate this undesired effect, two adjustable-RC buffers are added at the input of the PI. Finally,a 90nm CMOS phase interpolator,which can work in the frequency from 1GHz to 5GHz,is proposed. The power dissipation of the phase interpolator is lmW with a 1.2V power supply. Experiment results show that the phase interpolator has a monotone output phase and good linearity.
文摘A new low power quasi adiabatic logic,complementary pass transistor adiabatic logic (CPAL),is presented.The CPAL circuit is driven by a new three phase power clock,and its non adiabatic loss on output loads can be effectively reduced by using complementary pass transistor logic and transmission gates.Furthermore,the minimization of the energy consumption can be obtained by choosing the optimal size of bootstrapped nMOS transistors,thus it has more efficient energy transfer and recovery.A three phase power supply generator with a small control logic circuit and a single inductor is proposed.An 8 bit adder based on CPAL is designed and verified.With MOSIS 0 25μm CMOS technology,the CPAL adder consumes only 35% of the dissipated energy of a 2N 2N2P adder and is about 50% of the dissipated energy of a PFAL adder for clock rates ranging from 50 to 200MHz.
基金The National High Technology Research and Development Program of China (863 Program)(No. 2007AA01Z2a5)the National Natural Science Foundation of China (No. 60806027,61076073)Specialized Research Fund for the Doctoral Program of Higher Education (No.20090092120012)
文摘In order to make a 10 Gbit/s 2：1 half-rate multiplexer operate without external clocks, a 5 Gbit/s clock recovery （CR） circuit is needed to extract the desired clock from one input data. For the CR circuit, a 3-stage ring voltage-controlled oscillator （VCO） is employed to avoid an unreliable startup of a 2-stage VCO and a low oscillation frequency of a 4-stage VCO. A phase frequency detector （PFD） is used to expand the pull-in range to meet the wide tuning range of a VCO required by process-voltage-temperature （PVT） variation. SMIC 0. 18-μm CMOS technology is adopted and the core area is 170 μm ×270 μm. Measurements show that, under a 1.8 V supply voltage, it consumes only about 90 mW, and has an input sensitivity of less than 25 mV, an output single-ended swing of above 300 mV, a phase noise of - 114 dBc/Hz at 1 MHz offset and a pull-in range of 1 GHz.
文摘Based on the minimum settling time （MST） theory and step-response analysis of the second order system in active switched capacitor （SC） networks, a novel clock feedthrough frequency compensation （CFFC） method for a folded-cascode OTA is proposed. The damping factor r/is adjusted by using MOS capacitors to introduce clock feedthrough so that the OTA can obtain the MST state and thus achieve fast settling. Research results indicate that the settling time of the compensated OTA is reduced by 22.7% ;as the capacitor load varies from 0.5 to 2.5pF,the improved settling time increases approximately linearly from 3.62 to 4.46ns： for VGA application, fast settling can also be achieved by modifying the MOS capacitor value accordingly when the closed loop gain of the compensated OTA varies.
