Energy-band alignment of atomic layer deposited(HfO_2)_x(Al_2O_3)_(1-x) gate dielectrics on 4H-SiC

We study a series of（HfO2）x（Al2O3）1-x /4H-SiC MOS capacitors. It is shown that the conduction band offset of HfO2 is 0.5 e V and the conduction band offset of Hf AlO is 1.11–1.72 e V. The conduction band offsets of（Hf O2）x（Al2O3）1-x are increased with the increase of the Al composition, and the（HfO2）x（Al2O3）1-x offer acceptable barrier heights（〉 1 e V）for both electrons and holes. With a higher conduction band offset,（Hf O2）x（Al2O3）1-x/4H-SiC MOS capacitors result in a ～ 3 orders of magnitude lower gate leakage current at an effective electric field of 15 MV/cm and roughly the same effective breakdown field of ～ 25 MV/cm compared to HfO2. Considering the tradeoff among the band gap, the band offset, and the dielectric constant, we conclude that the optimum Al2O3 concentration is about 30% for an alternative gate dielectric in 4H-Si C power MOS-based transistors.

Phase control of magnetron sputtering deposited Gd_2O_3 thin films as high-κ gate dielectrics

Gd2O3 thin films as high-κ gate dielectrics were deposited directly on Si（001） substrates by magnetron sputtering at a pressure of 1.3 Pa and different temperatures. X-ray diffraction results revealed that all the films grown from 450 to 570 ℃ were crystalline, and the Gd2O3 thin films consisted of a mixture of cubic and monoclinic phases. The growth temperature was a critical parameter for the phase constituents and their relative amount. Low temperature was favorable for the formation of cubic phase while higher temperature gave rise to more monoclinic phase. All the Gd2O3 thin films grown from different temperatures exhibited acceptable electrical properties, such as low leakage current density （JL） of 10-5 A/cm^2 at zero bias with capacitance equivalent SiO2 thickness in the range of 6-13 nm. Through the comparison between films grown at 450 and 570 ℃, the existence of monoclinic phase caused an increase in JL by nearly one order of magnitude and a reduction of effective dielectric constant from 17 to 9.

The influence and explanation of fringing-induced barrier lowering on sub-100 nm MOSFETs with high-k gate dielectrics

The fringing-induced barrier lowering（FIBL） effect of sub-100 nm MOSFETs with high-k gate dielectrics is investigated using a two-dimensional device simulator.An equivalent capacitance theory is proposed to explain the physics mechanism of the FIBL effect.The FIBL effect is enhanced and the short channel performance is degraded with increasing capacitance.Based on equivalent capacitance theory,the influences of channel length,junction depth,gate/lightly doped drain（LDD） overlap length,spacer material and spacer width on FIBL is thoroughly investigated.A stack gate dielectric is presented to suppress the FIBL effect.

Aqueous-solution-driven HfGdO_x gate dielectrics for low-voltage-operated α-InGaZnO transistors and inverter circuits

In this work,a non-toxic and environmentally friendly aqueous-solution-based method has been adopted to prepare gadolinium-doped hafnium oxide(HfO2) gate dielectric thin films.By adjusting the gadolinium(Gd) doping concentration,the oxygen vacancy content,band offset,interface trap density,and dielectric constant of HfGdOx(HGO) thin films have been optimized.Results have confirmed that HGO thin films with Gd doping ratio of 15 at.% have demonstrated appropriate dielectric constant of 27.1 and lower leakage current density of 5.8×10-9 A cm-2.Amorphous indium-gallium-zinc oxide(α-IGZO) thin film transistors(TFTs) based on HGO thin film(Gd:15 at.%) as gate dielectric layer have exhibited excellent electrical performance,such as larger saturated carrier mobility(μsat) of 20.1 cm2 V-1 S-1,high on/off current ratio(Ion/Ioff) of ~108,smaller sub-threshold swing(SS) of 0.07 V decade-1,and a negligible threshold voltage shift(ΔVTH) of 0.08 V under positive bias stress(PBS) for 7200 s.To confirm its potential application in logic circuit,a resistor-loaded inverter based on HGO/α-IGZO TFTs has been constructed.A high voltage gain of 19.8 and stable full swing characteristics have been detected.As a result,it can be concluded that aqueous-solution-driven HGO dielectrics have potential application in high resolution flat panel displays and ultra-large-scale integrated logic circuits.

Challenges in Atomic-Scale Characterization of High-k Dielectrics and Metal Gate Electrodes for Advanced CMOS Gate Stacks

The decreasing feature sizes in complementary metal-oxide semiconductor （CMOS） transistor technology will require the replacement of SiO2 with gate dielectrics that have a high dielectric constant （high-k） because as the SiO2 gate thickness is reduced below 1.4 nm, electron tunnelling effects and high leakage currents occur in SiO2, which present serious obstacles to future device reliability. In recent years significant progress has been made on the screening and selection of high-k gate dielectrics, understanding their physical properties, and their integration into CMOS technology. Now the family of hafnium oxide-based materials has emerged as the leading candidate for high-k gate dielectrics due to their excellent physical properties. It is also realized that the high-k oxides must be implemented in conjunction with metal gate electrodes to get sufficient potential for CMOS continue scaling. In the advanced nanoscale Si-based CMOS devices, the composition and thickness of interfacial layers in the gate stacks determine the critical performance of devices. Therefore, detailed atomic- scale understandings of the microstructures and interfacial structures built in the advanced CMOS gate stacks, are highly required. In this paper, several high-resolution electron, ion, and photon-based techniques currently used to characterize the high-k gate dielectrics and interfaces at atomic-scale, are reviewed. Particularly, we critically review the research progress on the characterization of interface behavior and structural evolution in the high-k gate dielectrics by high-resolution transmission electron microscopy （HRTEM） and the related techniques based on scanning transmission electron microscopy （STEM）, including high-angle annular dark- field （HAADF） imaging （also known as Z-contrast imaging）, electron energy-loss spectroscopy （EELS）, and energy dispersive X-ray spectroscopy （EDS）, due to that HRTEM and STEM have become essential metrology tools for characterizing the dielectric gate stacks in the present and future generations of CMOS devices. In Section 1 of this review, the working principles of each technique are briefly introduced and their key features are outlined. In Section 2, microstructural characterizations of high-k gate dielectrics at atomic-scale by electron microscopy are critically reviewed by citing some recent results reported on high-k gate dielectrics. In Section 3, metal gate electrodes and the interfacial structures between high-k dielectrics and metal gates are discussed. The electron beam damage effects in high-k gate stacks are also evaluated, and their origins and prevention are described in Section 4. Finally, we end this review with personal perspectives towards the future challenges of atomic-scale material characterization in advanced CMOS gate stacks.

Novel electrical characterization for advanced CMOS gate dielectrics

This paper reviews the following electrical characterization techniques for measuring the microscopic bonding structures, impurities, and electrically active defects in advanced CMOS gate stacks： 1） inelastic electron tunneling spectroscopy （IETS）, 2） lateral profiling of threshold voltages, interface-trap density, and oxide charge density distributions along the channel of an MOSFET, and 3） pulse agitated substrate hot electron injection （PASHEI） technique for measuring trapping effects in the gate dielectric at low and modest gate voltages.

High-performance enhancement-mode AlGaN/GaN MOS-HEMTs with fluorinated stack gate dielectrics and thin barrier layer

We present high-performance enhancement-mode AlGaN/GaN metal-oxide-semiconductor highelectron mobility transistors（MOS-HEMTs） by a fluorinated gate dielectric technique.A nanolaminate of an Al_2O_3/La_xAl_（1-x）O_3/Al_2O_3 stack（x≈0.33） grown by atomic layer deposition is employed to avoid fluorine ions implantation into the scaled barrier layer.Fabricated enhancement-mode MOS-HEMTs exhibit an excellent performance as compared to those with the conventional dielectric-last technique,delivering a large maximum drain current of 916 mA/mm and simultaneously a high peak transconductance of 342 mS/mm.The balanced DC characteristics indicate that advanced gate stack dielectrics combined with buffered fluorine ions implantation have a great potential for high speed GaN E/D-mode integrated circuit applications.

Characteristics of high-quality HfSiON gate dielectric prepared by physical vapour deposition

This paper presents a method using simple physical vapour deposition to form high-quality hafnium silicon oxynitride （HfSiON） on ultrathin SiO2 buffer layer. The gate dielectric with 10A （1A = 0.1 nm） equivalent oxide thickness is obtained. The experimental results indicate that the prepared HfSiON gate dielectric exhibits good physical and electrical characteristics, including very good thermal stability up to 1000℃, excellent interface properties, high dielectric constant （k = 14） and low gate-leakage current （Ig = 1.9 × 10^-3 A/cm^2@Vg = Vfb - 1 V for EOT of 10 A）. TaN metal gate electrode is integrated with the HfSiON gate dielectric.The effective work function of TaN on HfSiON is 4.3 eV, meeting the requirements of NMOS for the metal gate. And, the impacts of sputtering ambient and annealing temperature on the electrical properties of HfSiON gate dielectric are investigated.

Electrical properties and reliability of HfO2 gate-dielectric MOS capacitors with trichloroethylene surface pretreatment

Trichloroethylene （TCE） pretreatment of Si surface prior to HfO2 deposition is employed to fabricate HfO2 gatedielectric MOS capacitors. Influence of this processing procedure on interlayer growth, HfO2/Si interface properties, gate-oxide leakage and device reliability is investigated. Among the surface pretreatments in NH3, NO, N2O and TCE ambients, the TCE pretreatment gives the least interlayer growths the lowest interface-state density, the smallest gate leakage and the highest reliability. All these improvements should be ascribed to the passivation effects of Cl2 and HC1 on the structural defects in the interlayer and at the interface, and also their gettering effects on the ion contamination in the gate dielectric.

Current Progress of Hf(Zr)-Based High-k Gate Dielectric Thin Films

With the continued downscaling of complementary metal-oxide-semiconductor field effect transistor dimensions, high-dielectric constant （high-k） gate materials, as alternatives to SiO2, have been extensively investigated. Hf （Zr）-based high-k gate dielectric thin films have been regarded as the most promising candidates for high-k gate dielectric according to the International Technology Roadmap for Semiconductor due to their excellent physical properties and performance. This paper reviews the recent progress on Hf （Zr）-based high-k gate dielectrics based on PVD （physical vapor deposition） process. This article begins with a survey of various methods developed for generating Hf （Zr）-based high-k gate dielectrics, and then mainly focuses on microstructure, synthesis, characterization, formation mechanisms of interfacial layer, and optical properties of Hf （Zr）-based high-k gate dielectrics. Finally, this review concludes with personal perspectives towards future research on Hf （Zr）-based high-k gate dielectrics.

High-k gate dielectric GaAs MOS device with LaON as interlayer and NH_3-plasma surface pretreatment

High-k gate dielectric Hf Ti ON Ga As metal-oxide–semiconductor（MOS） capacitors with La ON as interfacial passivation layer（IPL） and NH3- or N2-plasma surface pretreatment are fabricated, and their interfacial and electrical properties are investigated and compared with their counterparts that have neither La ON IPL nor surface treatment. It is found that good interface quality and excellent electrical properties can be achieved for a NH3-plasma pretreated Ga As MOS device with a stacked gate dielectric of Hf Ti ON/La ON. These improvements should be ascribed to the fact that the NH3-plasma can provide H atoms and NH radicals that can effectively remove defective Ga/As oxides. In addition, La ON IPL can further block oxygen atoms from being in-diffused, and Ga and As atoms from being out-diffused from the substrate to the high-k dielectric. This greatly suppresses the formation of Ga/As native oxides and gives rise to an excellent high-k/Ga As interface.

Excellent-Performance AlGaN/GaN Fin-MOSHEMTs with Self-Aligned Al_2O_3Gate Dielectric

A1GaN/GaN fin-shaped metal-oxide-semiconductor high-electron-mobility transistors （fin-MOSHEMTs） with dif- ferent fin widths （30Ohm and lOOnm） on sapphire substrates are fabricated and characterized. High-quality self-Migned Al2O3 gate dielectric underneath an 80-nm T-shaped gate is employed by Muminum self-oxidation, which induces 4 orders of magnitude reduction in the gate leakage current. Compared with conventional planar MOSHEMTs, short channel effects of the fabricated fin-MOSHEMTs are significantly suppressed due to the tri- gate structure, and excellent de characteristics are obtained, such as extremely fiat output curves, smaller drain induced barrier lower, smaller subthreshold swing, more positive threshold voltage, higher transconductance and higher breakdown voltage.

Electrical Characteristics of MOS Capacitors with HfTiON as Gate Dielectric

HfTiN film was deposited by co-reactive sputtering and then was annealed in dif-ferent gas ambients at temperature of 650 ℃ for 2 min to form HfTiON film. Capacitance-voltage and gate-leakage characteristics were investigated. The N2O-annealed sample exhibited small inter-face-state and oxide-charge densities, and enhanced reliability, which was attributed to the fact that nitridation could create strong Si≡N bonds to passivate dangling Si bonds and replaced strained Si-O bonds, thus forming a hardened dielectric/Si interface with high reliability. As a result, it is possible to prepare high-quality HfTiON gate dielectric of small-scaling CMOS devices in the industry-preferred N2O environment.

Experimental evaluation of interface states during time-dependent dielectric breakdown of GaN-based MIS-HEMTs with LPCVD-SiNχgate dielectric

We experimentally evaluated the interface state density of GaN MIS-HEMTs during time-dependent dielectric breakdown(TDDB).Under a high forward gate bias stress,newly increased traps generate both at the SiNx/AlGaN interface and the SiNx bulk,resulting in the voltage shift and the increase of the voltage hysteresis.When prolonging the stress duration,the defects density generated in the SiNx dielectric becomes dominating,which drastically increases the gate leakage current and causes the catastrophic failure.After recovery by UV light illumination,the negative shift in threshold voltage(compared with the fresh one)confirms the accumulation of positive charge at the SiNx/AlGaN interface and/or in SiNx bulk,which is possibly ascribed to the broken bonds after long-term stress.These results experimentally confirm the role of defects in the TDDB of GaN-based MIS-HEMTs.

A threshold voltage analytical model for high-k gate dielectric MOSFETs with fully overlapped lightly doped drain structures

We investigate the influence of voltage drop across the lightly doped drain（LDD） region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson＇s equation in the silicon and gate dielectric layers.The model can predict the fringing-induced barrier lowering effect and the short channel effect.It is also valid for non-LDD MOSFETs.Based on this model,the relationship between threshold voltage roll-off and three parameters,channel length,drain voltage and gate dielectric permittivity,is investigated.Compared with the non-LDD MOSFET,the LDD MOSFET depends slightly on channel length,drain voltage,and gate dielectric permittivity.The model is verified at the end of the paper.

Synthesis of thermally stable HfO_xN_y as gate dielectric for AlGaN/GaN heterostructure field-effect transistors

In this paper, we adopted thermally stable HfOxNy as gate dielectric for TiN/HfOxNy/A1GaN/GaN heterostructure field-effect transistors （HFETs） application. It demonstrated that the surface morphologies, composition, and optical properties of the HfOxNy films were dependent on oxygen flow rate in the O2/N2/mr mixture sputtering ambient. The obtained metal-oxide-semiconductor heterostructure field-effect transistors by depositing HfO2 and HfOxNy dielectric at different oxygen flow rates possessed a small hysteresis and a low leakage current. After post deposition annealing at 900 ℃, the device using HfOxNy dielectric operated normally with good pinch-off characteristics, while obvious degradation are observed for the HfO2 gated one at 600 ℃. This result shows that the HfOxNy dielectric is a promising candidate for the self-aligned gate process.

Analytical model including the fringing-induced barrier lowering effect for a dual-material surrounding-gate MOSFET with a high-κ gate dielectric

By solving Poisson＇s equation in both semiconductor and gate insulator regions in the cylindrical coordinates, an analytical model for a dual-material surrounding-gate （DMSG） metal-oxide semiconductor field-effect transistor （MOSFET） with a high-k gate dielectric has been developed. Using the derived model, the influences of fringing-induced barrier lowering （FIBL） on surface potential, subthreshold current, DIBL, and subthreshold swing are investigated. It is found that for the same equivalent oxide thickness, the gate insulator with high-k dielectric degrades the short-channel performance of the DMSG MOSFET. The accuracy of the analytical model is verified by the good agreement of its results with that obtained from the ISE three-dimensional numerical device simulator.

Current-collapse suppression and leakage-current decrease in AlGaN/GaN HEMT by sputter-TaN gate-dielectric layer

In this paper, we explore the electrical characteristics of high-electron-mobility transistors(HEMTs) using a TaN/AlGaN/GaN metal insulating semiconductor(MIS) structure. The high-resistance tantalum nitride(TaN) film prepared by magnetron sputtering as the gate dielectric layer of the device achieved an effective reduction of electronic states at the TaN/AlGaN interface, and reducing the gate leakage current of the MIS HEMT, its performance was enhanced. The HEMT exhibited a low gate leakage current of 2.15 × 10^(-7) mA/mm and a breakdown voltage of 1180 V. Furthermore, the MIS HEMT displayed exceptional operational stability during dynamic tests, with dynamic resistance remaining only 1.39 times even under 400 V stress.

Improved Performance of Organic Thin Film Transistor with an Inorganic Oxide/Polymer Double-Layer Insulator

We employ the Ta2Os/PVP （poly-4-vinylphenol） double-layer gate insulator to improve the performance of pentacene thin-film transistors. It is found that the double-layer insulator has low leakage current, smooth surface and considerably high capacitance. Compared to Ta205 insulator layers, the device with the Ta2Os/PVP doublelayer insulator exhibits an enhancement of the field-effect mobility from 0.21 to 0.54 cm2/Vs, and the decreasing threshold voltage from 4.38 V to -2.5 V. The results suggest that the Ta2Os/PVP double-layer insulator is a potential gate insulator for fabricating OTFTs with good electrical performance.

Electrical Properties of Sputter-deposited ZrO2-based Pt/ZrO_2/Si Capacitors

Pt/ZrO2/Si sandwich structures where ZrO2 is deposited by radio frequency （r.f.） magnetron sputtering using a Zr target in an atmosphere of O2/Ar gas mixture, were fabricated and the effects of the O2/Ar flow ratio in the reactive sputtering process, the annealing temperature, the ZrO2 film thickness on the structure, the surface roughness of ZrO2 films and the electric properties of Pt/ZrO2/Si metal-oxide-semiconductor （MOS） capacitors were investigated. The optimum process parameters of the Pt/ZrO2/Si capacitor based on reactively sputtered-ZrO2 determined in such a way as the capacitance is maximized and the leakage current, the oxide charge, and the interface trap density are minimized that is the O2/Ar flow ratio of 1.5, the annealing temperature of 800℃, and the film thickness of 10 nm. Also the conduction mechanism in the Pt/ZrO2/Si capacitor has been discussed.