Modeling analysis of thin fully depleted SOICMOS technology has been done. Using ISETCAD software,the high temperature characteristics of an SOICMOS transistor were simulated in the temperature range of from 300 to 60...Modeling analysis of thin fully depleted SOICMOS technology has been done. Using ISETCAD software,the high temperature characteristics of an SOICMOS transistor were simulated in the temperature range of from 300 to 600K, and the whole circuit of a laser range finder was simulated with Verilog software. By wafer pro- cessing,a circuit of a laser range finder with complete function and parameters working at high temperatures has been developed. The simulated results agree with the test results. The test of the circuit function and parameters at normal and high temperature shows the realization of an SOICMOS integrated circuit with low power dissipation and high speed, which can be applied in laser range finding. By manufacturing this device, further study on high temperature characteristics of shorter channel SOICMOS integrated circuits can be conducted.展开更多
A Schottky gate resonant tunneling transistor （SGRTT） is fabricated. Relying on simulation by ATLAS software,we find that the gate voltages can be used to control the current of SGRTT when the emitter terminal is gr...A Schottky gate resonant tunneling transistor （SGRTT） is fabricated. Relying on simulation by ATLAS software,we find that the gate voltages can be used to control the current of SGRTT when the emitter terminal is grounded and a positive bias voltage is applied to the collector terminal. When the collector terminal is grounded, the gate voltages can control the peak voltage. As revealed by measurement results, the reason is that the gate voltages and the electric field distribution on emitter and collector terminal change the distribution of the depletion region.展开更多
The monolithic integration of enhancement- and depletion-mode （E/D-mode） InGaP/AIGaAs/InGaAs pseudomorphic high electron mobility transistors （PHEMTs） with a 1.0μm gate length is presented. Epilayers are grown on...The monolithic integration of enhancement- and depletion-mode （E/D-mode） InGaP/AIGaAs/InGaAs pseudomorphic high electron mobility transistors （PHEMTs） with a 1.0μm gate length is presented. Epilayers are grown on SI GaAs substrates using MBE. For this structure, a mobility of 5410cm^2/（V · s） and a sheet density of 1.34 × 10^12 cm^-2 are achieved at room temperature. During the gate fabrication of E/D-mode PHEMTs,a novel twostep technology is applied. The devices with a gate dimension of 1μm × 100μm exhibit good DC and RF performances. Threshold voltages of 0. 2 and -0. 4V,maximum drain current densities of 300 and 340mA/mm,and extrinsic transconductances of 350 and 300mS/mm for E- and D-mode PHEMTs are obtained, respectively. The reverse gatedrain breakdown voltage is -14V for both E- and D-mode. Current-gain cutoff frequencies of 10. 3 and 12.4GHz and power-gain cutoff frequencies of 12.8 and 14.7GHz for E- and D-mode are reported, respectively.展开更多
A novel device, lateral PIN photodiode gated by transparent electrode （LPIN PD-GTE） fabricated on fully-depleted SOI film was proposed. ITO film was adopted in the device as gate electrode to reduce the light absorp...A novel device, lateral PIN photodiode gated by transparent electrode （LPIN PD-GTE） fabricated on fully-depleted SOI film was proposed. ITO film was adopted in the device as gate electrode to reduce the light absorption. Thin Si film was fully depleted under gate voltage to achieve low dark current and high photo4o-dark current ratio. The model of gate voltage was obtained and the numerical simulations were presented by ATLAS. Current-voltage characteristics of LPIN PD-GTE obtained in dark （dark current） and under 570 nm illumination （photo current） were studied to achieve the greatest photo-to-dark current ratio for active channel length from 2 to 12 /am. The results show that the photo-to-dark current ratio is 2.0×10^7, with dark current of around 5×10^-4 pA under VGK=0.6 V, PrN=5 mW/cm2, for a total area of 10μm×10μm in fully depleted SOI technology. Thus, the LPIN PD-GTE can be suitable for high-grade photoelectric systems such as blue DVD.展开更多
文摘Modeling analysis of thin fully depleted SOICMOS technology has been done. Using ISETCAD software,the high temperature characteristics of an SOICMOS transistor were simulated in the temperature range of from 300 to 600K, and the whole circuit of a laser range finder was simulated with Verilog software. By wafer pro- cessing,a circuit of a laser range finder with complete function and parameters working at high temperatures has been developed. The simulated results agree with the test results. The test of the circuit function and parameters at normal and high temperature shows the realization of an SOICMOS integrated circuit with low power dissipation and high speed, which can be applied in laser range finding. By manufacturing this device, further study on high temperature characteristics of shorter channel SOICMOS integrated circuits can be conducted.
文摘A Schottky gate resonant tunneling transistor （SGRTT） is fabricated. Relying on simulation by ATLAS software,we find that the gate voltages can be used to control the current of SGRTT when the emitter terminal is grounded and a positive bias voltage is applied to the collector terminal. When the collector terminal is grounded, the gate voltages can control the peak voltage. As revealed by measurement results, the reason is that the gate voltages and the electric field distribution on emitter and collector terminal change the distribution of the depletion region.
文摘The monolithic integration of enhancement- and depletion-mode （E/D-mode） InGaP/AIGaAs/InGaAs pseudomorphic high electron mobility transistors （PHEMTs） with a 1.0μm gate length is presented. Epilayers are grown on SI GaAs substrates using MBE. For this structure, a mobility of 5410cm^2/（V · s） and a sheet density of 1.34 × 10^12 cm^-2 are achieved at room temperature. During the gate fabrication of E/D-mode PHEMTs,a novel twostep technology is applied. The devices with a gate dimension of 1μm × 100μm exhibit good DC and RF performances. Threshold voltages of 0. 2 and -0. 4V,maximum drain current densities of 300 and 340mA/mm,and extrinsic transconductances of 350 and 300mS/mm for E- and D-mode PHEMTs are obtained, respectively. The reverse gatedrain breakdown voltage is -14V for both E- and D-mode. Current-gain cutoff frequencies of 10. 3 and 12.4GHz and power-gain cutoff frequencies of 12.8 and 14.7GHz for E- and D-mode are reported, respectively.
基金Project(61040061) supported by the National Natural Science Foundation of ChinaProject supported by Hunan Provincial Innovation Foundation for Postgraduate Students,China
文摘A novel device, lateral PIN photodiode gated by transparent electrode （LPIN PD-GTE） fabricated on fully-depleted SOI film was proposed. ITO film was adopted in the device as gate electrode to reduce the light absorption. Thin Si film was fully depleted under gate voltage to achieve low dark current and high photo4o-dark current ratio. The model of gate voltage was obtained and the numerical simulations were presented by ATLAS. Current-voltage characteristics of LPIN PD-GTE obtained in dark （dark current） and under 570 nm illumination （photo current） were studied to achieve the greatest photo-to-dark current ratio for active channel length from 2 to 12 /am. The results show that the photo-to-dark current ratio is 2.0×10^7, with dark current of around 5×10^-4 pA under VGK=0.6 V, PrN=5 mW/cm2, for a total area of 10μm×10μm in fully depleted SOI technology. Thus, the LPIN PD-GTE can be suitable for high-grade photoelectric systems such as blue DVD.
