安徽花鼓灯传统舞鞋“衬子”的手工制作工艺

通过实际考察、寻访,剖析了花鼓灯舞鞋"衬子"手工制作工艺的田野调查,恢复再现传统舞鞋"衬子"制作的原材料、制作工具以及纯手工工艺制作的全过程,为后人留下祖辈艺术精髓的复原资料,使花鼓灯艺术常演常新,代代传承。

以景衬情的“衬”

朱雀桥边野草花.乌衣巷口夕阳斜。旧时王谢堂前燕,飞入寻常百姓家。这是唐朝诗人刘禹锡感叹历史兴衰的著名诗作《乌衣巷》,大家比较熟悉。诗人描写了这样一幅画面:过去十分繁华的朱雀桥如今野草丛生,野草丛中开着几朵零星的花;曾经居住过显赫人物的乌衣巷。

Effect of substrate temperature and oxygen plasma treatment on the properties of magnetron-sputtered CdS for solar cell applications

Cadmium sulfide(CdS)is an n-type semiconductor with excellent electrical conductivity that is widely used as an electron transport material(ETM)in solar cells.At present,numerous methods for preparing CdS thin films have emerged,among which magnetron sputtering(MS)is one of the most commonly used vacuum techniques.For this type of technique,the substrate temperature is one of the key deposition parameters that affects the interfacial properties between the target film and substrate,determining the specific growth habits of the films.Herein,the effect of substrate temperature on the microstructure and electrical properties of magnetron-sputtered CdS(MS-CdS)films was studied and applied for the first time in hydrothermally deposited antimony selenosulfide(Sb_(2)(S,Se)_(3))solar cells.Adjusting the substrate temperature not only results in the design of the flat and dense film with enhanced crystallinity but also leads to the formation of an energy level arrangement with a Sb_(2)(S,Se)_(3)layer that is more favorable for electron transfer.In addition,we developed an oxygen plasma treatment for CdS,reducing the parasitic absorption of the device and resulting in an increase in the short-circuit current density of the solar cell.This study demonstrates the feasibility of MS-CdS in the fabrication of hydrothermal Sb_(2)(S,Se)_(3)solar cells and provides interface optimization strategies to improve device performance.

Application of optimized random forest regressors in predicting maximum principal stress of aseismic tunnel lining

Using flexible damping technology to improve tunnel lining structure is an emerging method to resist earthquake disasters,and several methods have been explored to predict mechanical response of tunnel lining with damping layer.However,the traditional numerical methods suffer from the complex modelling and time-consuming problems.Therefore,a prediction model named the random forest regressor(RFR)is proposed based on 240 numerical simulation results of the mechanical response of tunnel lining.In addition,circle mapping(CM)is used to improve Archimedes optimization algorithm(AOA),reptile search algorithm(RSA),and Chernobyl disaster optimizer(CDO)to further improve the predictive performance of the RFR model.The performance evaluation results show that the CMRSA-RFR is the best prediction model.The damping layer thickness is the most important feature for predicting the maximum principal stress of tunnel lining containing damping layer.This study verifies the feasibility of combining numerical simulation with machine learning technology,and provides a new solution for predicting the mechanical response of aseismic tunnel with damping layer.

MOCVD-Grown AlGaN/AlN/GaN HEMT Structure with High Mobility GaN Thin Layer as Channel on SiC

AlGaN/AlN/GaN high electron mobility transistor （HEMT） structures with a high-mobility GaN thin layer as a channel are grown on high resistive 6H-SiC substrates by metalorganic chemical vapor deposition. The HEMT structure exhibits a typical two-dimensional electron gas （2DEG） mobility of 1944cm^2/（V·s） at room temperature and 11588cm^2/（V ·s） at 80K with almost equal 2DEG concentrations of about 1.03 × 10^13 cm^-2. High crystal quality of the HEMT structures is confirmed by triple-crystal X-ray diffraction analysis. Atomic force microscopy measurements reveal a smooth AlGaN surface with a root-mean-square roughness of 0.27nm for a scan area of 10μm × 10μm. HEMT devices with 0.8μm gate length and 1.2mm gate width are fabricated using the structures. A maximum drain current density of 957mA/mm and an extrinsic transconductance of 267mS/mm are obtained.

ZnO Films Synthesized by Solid-Source Chemical Vapor Deposition with c-Axis Parallel to Substrate

ZnO films with c -axis parallel to the substrate are reported.ZnO films are synthesized by solid-source chemical vapor deposition,a novel CVD technique,using zinc acetate dihydrate (solid) as the source material.The properties are characterized by X-ray diffraction,atomic force microscopy and transmission spectra.The parallel oriented ZnO films with mixed orientation for (100) and (110) planes are achieved on glass at the substrate temperature of 200℃ and the source temperature of 280℃,and a qualitative explanation is given for the forming of the mixed orientation.AFM images show that the surface is somewhat rough for the parallel oriented ZnO films.The transmission spectrum exhibits a high transmittance of about 85% in the visible region and shows an optical band gap about 3.25eV at room temperature.

Novel Substrate pn Junction Isolation for RF Integrated Inductors on Silicon

A new method for reducing the substrate rated losses of integrated spiral inductors is presented.The method is to block the eddy currents induced by spiral inductors by directly forming pn junction isolation in the Si substrate. The substrate pn junction can be realized by using the standard silicon technologies without any additional processing steps.Integrated inductors on silicon are designed and fabricated. S parameters of the inductor based equivalent circuit are investigated and the inductor parameters are calculated.The impacts of the substrate pn junction isolation on the inductor quality factor are studied.The experimental results show that substrate pn junction isolation in certain depth has achieved a significant improvement.At 3GHz,the substrate pn junction isolation increases the inductor quality factor by 40%.

Fabrication and Characterization of Strained Si Material Using SiGe Virtual Substrate for High Mobility Devices

The fabrication and characterization of strained-Si material grown on a relaxed Si0.79 Ge0.21/graded Si1-x- Gex/Si virtual substrate, using reduced pressure chemical vapor deposition, are presented. The Ge concentration of the constant composition SiGe layer and the grading rate of the graded SiGe layer are estimated with double-crystal X-ray diffraction and further confirmed by SIMS measurements. The surface root mean square roughness of the strained Si cap layer is 2.36nm,and the strain is about 0.83% as determined by atomic force microscopy and Raman spectra, respectively. The threading dislocation density is on the order of 4 × 10^4cm^-2. Furthermore, it is found that the stress in the strained Si cap layer is maintained even after the high thermal budget process, nMOSFET devices are fabricated and measured in strained-Si and unstrained bulk-Si channels. Compared to the co-processed bulk-Si MOSFETs at room temperature,a significant low vertical field mobility enhancement of about 85% is observed in the strained-Si devices.

Variable-based Ramberg-Osgood constitutive model of power spinning bushing

The influences of power spinning process parameters on the mechanical properties of spinning parts were analyzed with an SXD100/3-CNC numerical control power spinning machine.The unidirectional tensile tests were carried out.Based on the experimental data,a ternary quadratic regression equation was established by orthogonal experiment.The Ramberg-Osgood constitutive model of tin-bronze connecting rod bushing was obtained.Referred to the constitutive relation of macroscopic incremental,the incremental elastoplastic constitutive relation of spinning parts was deduced based on the Mises yield criterion and kinematic hardening model.The results can be applied to the elastoplastic analysis in finite element numerical simulation.

Strained-Si pMOSFETs on Very Thin Virtual SiGe Substrates

Strained-Si pMOSFETs on very thin relaxed virtua l SiGe substrates are presented.The 240nm relaxed virtual Si 0.8 Ge 0.2 layer on 100nm low-temperature Si(LT-Si) is grown on Si(100) substrates by molecular beam epitaxy.LT-Si buffer layer is used to release stress of the SiGe layer so as to make it relaxed.DCXRD,AFM,and TEM measurements indicate that the strain relaxed degree of SiGe layer is 85%,RMS roughness is 1.02nm,and threading dislocation density is at most 107cm -2 .At room temperature,a maximum hole mobility of strained-Si pMOSFET is 140cm2/(V·s).Device performance is comparable to that of devices achieved on several microns thick relaxed virtual SiGe substrates.

Some factors controlling diffusive transportof potassium ion through clayey soils

To investigate the potential use of two Japanese regional clayey soils, named Ariake clay and Akaboku soil, as soil barrier materials, a series of laboratory diffusion tests are presented. Using an available computer program Pollute V6.3, the effective diffusion coefficients of K^＋ of the soils were back-calculated from the diffusion tests. It is found that the Ariake clay has a larger effective diffusion coefficient than the Akaboku soil, indicating that the Ariake clay may provide a better diffusion barrier. A comparison of the effective diffusion coefficients between the single-salt solution condition and the multi-salt solution condition indicates that soils have higher effective diffusion coefficients under the former condition. It is suggested to use miscible solution close to landfill leachates for determining effective diffusion coefficients of specified chemical species for a practical design.

Poisoning-free effect of calcium on grain refinement of Mg-3%Al alloy containing trace Fe by carbon inoculation

Mg-3%Al alloy was modified by combining Ca addition with carbon inoculation. The effects of Fe addition and addition sequence on the grain refinement were investigated. A higher grain refining efficiency could be obtained for the Mg-Al alloy modified by combining Ca addition with carbon inoculation. Fe addition and addition sequence had no obvious effect on the grain refinement. Ca addition could effectively avoid grain-coarsening resulting from Fe in the carbon-inoculated Mg-Al alloy. The Al-C-O particles, actually being Al4C3, should act as potent substrates for a-Mg grains in the sample treated by combining Ca addition with carbon inoculation. However, the duplex-phase particles of AI4C3 coated on Al-Fe or Al-C-Fe should be the potent substrates for a-Mg grains if Fe existed in the Mg-Al melt. Ca addition can contribute to the formation of the particles of Al4C3 coated on Al-Fe or Al-C-Fe, regardless of the Fe addition sequence. The poisoning effect of Fe was effectively inhibited in the carbon-inoculated of Mg-Al alloy due to Ca addition, namely, Ca has a poisoning-free effect.

New Lateral Super Junction MOSFETs with n^+-Floating Layer on High-Resistance Substrate

A new super junction LDMOST structure that suppresses the substrate-assisted depletion effect is designed with an n^＋-floating layer embedded in the high-resistance p-type substrate by implanting phosphor or arsenic. This effect results from a charge imbalance between the n-type and p-type pillars when the n-type pillars are depleted by p-type substrate. The high electric field around the drain is reduced by the n^＋-floating layer due to the REBULF effect,which causes the redistribution of the bulk electric field in the drift region,and thus the substrate supports more biases. The new structure features high breakdown voltage, low on-resistance,and charge balance in the drift region.

Realizing High Breakdown Voltage SJ-LDMOS on Bulk Silicon Using a Partial n-Buried Layer

A new design concept is proposed to eliminate the substrate-assisted depletion effect that significantly degrades the breakdown voltage （BV） of conventional super junction-LDMOS. The key feature of the new concept is that a partial buried layer is implemented which compensates for the charge interaction between the p-substrate and SJ region,realizing high breakdown voltage and low on-resistance. Numerical simulation results indicate that the proposed device features high breakdown voltage,low on-resistance,and reduced sensitivity to doping imbalance in the pillars. In addition, the proposed device is compatible with smart power technology.

Heteroepitaxial Growth of 3C-SiC Films on Maskless Patterned Silicon Substrates

Heteroepitaxial growth of 3C-SiC on patterned Si substrates by low pressure chemical vapor deposition （LPCVD） has been investigated to improve the crystal quality of 3C-SiC films. Si substrates were patterned with parallel lines,1 to 10μm wide and spaced 1 to 10μm apart,which was carried out by photolithography and reactive ion etching. Growth behavior on the patterned substrates was systematically studied by scanning electron microscopy （SEM）. An airgap structure and a spherical shape were formed on the patterned Si substrates with different dimensions. The air gap formed after coalescence reduced the stress in the 3C-SiC films, solving the wafer warp and making it possible to grow thicker films. XRD patterns indicated that the films grown on the maskless patterned Si substrates were mainly composed of crystal planes with （111） orientation.

Preparation of 50mm 3C-SiC/Si(111) as Substrates Suited for Ⅲ-Nitrides

mm SiC films with high electrical uniformity a re grown on Si(111) by a newly developed vertical low-pressure chemical vapor dep osition (LPCVD) reactor.Both in-situ n- and p-type doping of 3C-SiC are achi eved by intentional introduction of ammonia and boron into the precursor gases.T he dependence of growth rate and surface morphology on the C/Si ratio and optimi zed growth conditions is obtained.The best electrical uniformity of 50mm 3C-SiC films obtained by non-contact sheet resistance measurement is ±2.58%.GaN fil ms are grown atop the as-grown 3C-SiC/Si(111) layers using molecular beam epit axy (MBE).The data of both X-ray diffraction and low temperature photoluminesc e nce of GaN/3C-SiC/Si(111) show that 3C-SiC is an appropriate substrate or buff er layer for the growth of Ⅲ-nitrides on Si substrates with no cracks.

Low-Cost, High-Reflectivity Silicon-on-Reflector for Optoelectronic Device Application

A silicon on reflector (SOR) substrate containing a thin crystal silicon layer and a buried Si/SiO 2 Bragg reflector is reported. The substrate, which is applied to optoelectronic devices, is fabricated by using Si based sol gel sticking and smart cut techniques. The reflectivity of the SOR substrate is close to unity at 1 3μm's wavelength under the normal incidence.

Patterned Dual pn Junctions Restraining Substrate Loss of an On-Chip Inductor

Dual pn junctions in lateral and vertical directions are formed by diffusing the p^＋ on the patterned n-well in standard CMOS technology, which are inserted under the inductor in order to reduce the currents in the substrate induced by the electromagnetic field from the inductor. The thickness of high resistance is not equivalent to the width of the depletion region of the vertical pn junctions,but the depth of the bottom pn junction in the substrate are both proposed and validated. For the first time, through the grounded p^＋-diffusion layer shielding the suhstrate from the electric field of the inductor, the width of the depletion regions of the lateral and vertical pn junctions are changed by increasing the voltage applied to the n wells. The quality factor is improved or reduced with the thickness of high resistance by 19%. This phenomenon validates the theory that the pn junction substrate isolation can reduce the loss caused by the currents in the substrate induced by the electromagnetic field from the inductor.

Homoepitaxial Growth and Characterization of 4H-SiC Epilayers by Low-Pressure Hot-Wall Chemical Vapor Deposition

Horizontal air-cooled low-pressure hot-wall CVD (LP-HWCVD) system is developed to get highly qualitical 4H-SiC epilayers.Homoepitaxial growth of 4H-SiC on off-oriented Si-face (0001) 4H-SiC substrates is performed at 1500℃ with a pressure of 1.3×103Pa by using the step-controlled epitaxy.The growth rate is controlled to be about 1.0μm/h.The surface morphologies and structural and optical properties of 4H-SiC epilayers are characterized with Nomarski optical microscope,atomic force microscopy (AFM),X-ray diffraction,Raman scattering,and low temperature photoluminescence (LTPL).N-type 4H-SiC epilayers are obtained by in-situ doping of NH 3 with the flow rate ranging from 0.1 to 3sccm.SiC p-n junctions are obtained on these epitaxial layers and their electrical and optical characteristics are presented.The obtained p-n junction diodes can be operated at the temperature up to 400℃,which provides a potential for high-temperature applications.

A 12-Channel,30Gb/s,0.18μm CMOS Front-End Amplifier for Parallel Optic-Fiber Receivers

This paper presents a 12-channel,30Gb/s front-end amplifier realized in standard 0.18μm CMOS technology for parallel optlc-fiber receivers. In order to overcome the problem of inadequate bandwidth caused by the large parasitical capacitor of CMOS photo-detectors,a regulated-cascode structure and noise optimization are used in the design of the transimpedance amplifier. The experimental results indicate that, with a parasitical capacitance of 2pF,a single channel is able to work at bite rates of up to 2.5Gb/s,and a clear eye diagram is obtained with a 0. 8mVpp input. Furthermore, an isolation structure combined with a p^＋ guard.ring （PGR）, an n^＋ guard-ring （NGR）,and a deep-n-well （DNW） for parallel amplifier is also presented. Taking this combined structure, the crosstalk and the substrate noise coupling have been effectively reduced. Compared with the isolation of PGR or PGR ＋ NGR,the measured results show that the isolation degree of this structure is improved by 29.2 and 8. ldB at 1GHz,and by 8. 1 and 2. 5dB at 2GHz,respectively. With a 1.8V supply,each channel of the front-end amplifier consumes a DC power of 85mW,and the total power consumption of 12 channels is about 1W.