Correction of microwave pulse reflection by digital filters in superconducting quantum circuits

Reducing the control error is vital for high-fidelity digital and analog quantum operations.In superconducting circuits,one disagreeable error arises from the reflection of microwave signals due to impedance mismatch in the control chain.Here,we demonstrate a reflection cancelation method when considering that there are two reflection nodes on the control line.We propose to generate the pre-distortion pulse by passing the envelopes of the microwave signal through digital filters,which enables real-time reflection correction when integrated into the field-programmable gate array(FPGA).We achieve a reduction of single-qubit gate infidelity from 0.67%to 0.11%after eliminating microwave reflection.Real-time correction of microwave reflection paves the way for precise control and manipulation of the qubit state and would ultimately enhance the performance of algorithms and simulations executed on quantum processors.

Investigation on Analog and Digital Modulations Recognition Using Machine Learning Algorithms

In the field of radiocommunication, modulation type identification is one of the most important characteristics in signal processing. This study aims to implement a modulation recognition system on two approaches to machine learning techniques, the K-Nearest Neighbors (KNN) and Artificial Neural Networks (ANN). From a statistical and spectral analysis of signals, nine key differentiation features are extracted and used as input vectors for each trained model. The feature extraction is performed by using the Hilbert transform, the forward and inverse Fourier transforms. The experiments with the AMC Master dataset classify ten (10) types of analog and digital modulations. AM_DSB_FC, AM_DSB_SC, AM_USB, AM_LSB, FM, MPSK, 2PSK, MASK, 2ASK, MQAM are put forward in this article. For the simulation of the chosen model, signals are polluted by the Additive White Gaussian Noise (AWGN). The simulation results show that the best identification rate is the MLP neuronal method with 90.5% of accuracy after 10 dB signal-to-noise ratio value, with a shift of more than 15% from the k-nearest neighbors’ algorithm.

Design of a 14-Bit 1 MS/s Successive Approximation Analog-to-Digital Converter

A 14-bit successive approximation analog-to-digital converter (SAR ADC) with capacitive calibration has been designed based on the SMIC. 18 μm CMOS process. The overall architecture is in fully differential form to eliminate the effect caused by common mode noise. Meanwhile, the digital-to-analog converter (DAC) is a two-stage structure, which can greatly reduce the area of the capacitor array compared with the traditional DAC structure. The capacitance calibration module is mainly divided into the mismatch voltage acquisition phase and the calibration code backfill phase, which effectively reduces the impact of the DAC mismatch on the accuracy of the SAR ADC. The design of this paper is based on cadence platform simulation verification, simulation results show that when the sampling rate is 1 MS/s, the power supply voltage is 5 V and the reference voltage is 4.096 V, the effective number of bits (ENOB) of the ADC is 13.49 bit, and the signal-to-noise ratio (SNR) is 83.3 dB.

TRANSIENT CHARACTERISTIC ANALYSIS OF HIGH TEMPERATURE CMOS DIGITAL INTEGRATED CIRCUITS

This paper analyses the transient characteristics of high temperature CMOS inverters and gate circuits, and gives the computational formulas of their rise time, fall time and delay time. It may be concluded that the transient characteristics of CMOS inverters and gate circuits deteriorate due to the reduction of carrier mobilities and threshold voltages of MOS transistors and the increase of leakage currents of MOS transistors drain terminal pn junctions. The calculation results can explain the experimental phenomenon.

Digital synthesis of programmable photonic integrated circuits

Programmable photonic waveguide meshes can be programmed into many different circuit topologies and thereby provide a variety of functions.Due to the complexity of the signal routing in a general mesh,a particular synthesis algorithm often only accounts for a specific function with a specific cell configuration.In this paper,we try to synthesize the programmable waveguide mesh to support multiple configurations with a more general digital signal processing platform.To show the feasibility of this technique,photonic waveguide meshes in different configurations(square,triangular and hexagonal meshes)are designed to realize optical signal interleaving with arbitrary duty cycles.The digital signal processing(DSP)approach offers an effective pathway for the establishment of a general design platform for the software-defined programmable photonic integrated circuits.The use of well-developed DSP techniques and algorithms establishes a link between optical and electrical signals and makes it convenient to realize the computer-aided design of optics–electronics hybrid systems.

Reconfigurable Digital Circuits Based on Chip Expander with Integrated Temperature Regulation

This article is dealing with a development of custom chip expander platform with the possibility of accurate temperature control and integration of additional silicon-based features. Such platform may serve as a useful tool which facilitates the burdens connected with measurement and analysis tasks of experimental semiconductor structures. The devised solution provides the functionality of carrier substrate (Al2O3 compound) with CTE compatibility to the experimental silicon chip and is fully customizable with respect to a particular chip. It also allows achieving an easy fan-out of small-diameter chip terminals into a larger, more convenient area and placement of chip specimens conveniently into space-constrained chamber of the AFM microscopes, probe stations, etc. Real application of the developed chip expander platform is demonstrated in context of digital reconfigurable circuits based on polymorphic electronics. In this case the chip expander with attached polymorphic chip REPOMO is thermally stabilized at an ambient temperature level up to approximately 135。C and its sensitivity to this phenomenon is demonstrated.

Wavelet neural network based fault diagnosis in nonlinear analog circuits

The theories of diagnosing nonlinear analog circuits by means of the transient response testing are studled. Wavelet analysis is made to extract the transient response signature of nonlinear circuits and compress the signature dada. The best wavelet function is selected based on the between-category total scatter of signature. The fault dictionary of nonlinear circuits is constructed based on improved back-propagation（BP） neural network. Experimental results demonstrate that the method proposed has high diagnostic sensitivity and fast fault identification and deducibility.

A Signal-Flow Driven Automatic Physical Synthesis Methodology for Analog Circuits

This paper introduces a novel automatic physical synthesis methodology for analog circuits based on the signal-flow analysis.Circuit analysis sub-system adopts the newly advanced methodology,circuit topology analysis,and circuit sensitivity analysis to generate layout constraints and control performance degradations.Considering the heuristic information about signal-flow,complexity of the methodology is less than the pure performance-driven methodology.And then these constraints are implemented in device generation,placement,and routing sub-systems separately,which makes the different constraints be satisfied at most easily implemented stages.Excellent circuit performance obtained by the methodology is demonstrated by practical circuit examples.

Digitalization of inverting filter shaping circuit for nuclear pulse signals

In the design of filter shaping circuits for nuclear pulse signals,inverting filter shaping circuits perform better than non-inverting filter shaping circuits.Because these circuits facilitate changing the phase of a pulse signal,they are widely used in processing nuclear pulse signals.In this study,the transfer functions of four types of inverting filter shaping circuits,namely the common inverting filter shaping,improved inverting filter shaping,multiple feedback low-pass filter shaping,and third-order multiple feedback low-pass filter shaping,in the Laplacian domain,are derived.We establish the numerical recursive function models and digitalize the four circuits,obtain the transfer functions in the Z domain,and analyze the filter performance and amplitude-frequency response characteristics in the frequency domain.Based on the actual nuclear pulse signal of the Si-PIN detector,we realize four types of inverting digital shaping.The results show that under the same shaping parameters,the common inverting digital shaping has better amplitude extraction characteristics,the third-order multiple feedback low-pass digital shaping has better noise suppression performance,and the multiple feedback digital shaping takes into account both pulse amplitude extraction and noise suppression performance.

Digital仿真测试在改进数字逻辑课程教学中的应用探究--基于与Logisim软件的比较

针对数字逻辑课程教材中的一处错误,提出使用Digital仿真软件进行测试的改进方案。分析表明:Digital仿真软件能用于组合逻辑电路与时序逻辑电路的测试;其不仅可使用真值表实现测试,还可用测试语句构建大规模的复杂测试用例,更适用于数字逻辑课程教学中设计题目的测试。进一步与Logisim软件比较表明:Digital软件测试功能更强,波形观察方便,更有助于实验和测试;考虑了电源和接地、外接端子均为双向连接,Digital软件所构建和仿真的电路更加符合实际;其RAM器件类型更多,有助于仿真完整的计算机系统。据此提出,在数字电路和计算机组成原理等硬件课程教学中推广使用Digital软件。

Testing Cross-Talk Induced Delay Faults in Digital Circuit Based on Transient Current Analysis

The delay fault induced by cross-talk effect is one of the difficult problems in the fault diagnosis of digital circuit. An intelligent fault diagnosis based on IDDT testing and support vector machines （SVM） classifier was proposed in this paper. Firstly, the fault model induced by cross-talk effect and the IDDT testing method were analyzed, and then a delay fault localization method based on SVM was presented. The fault features of the sampled signals were extracted by wavelet packet decomposition and served as input parameters of SVM classifier to classify the different fault types. The simulation results illustrate that the method presented is accurate and effective, reaches a high diagnosis rate above 95%.

Application of digital driving circuit in arc welding power source based on HCPL-316J

The digitalization of arc welding power source mainly depends on the digitalization of arc welding inverter,so that main circuit and controlling system can give full play to advantages.Digital switching control makes main circuit digital and DSP and/or MCU makes controlling system,digital.So IGBT driving circuit,as a tie of main circuit and controlling system,should also be got digitalized.Thus,a digital driving circuit based on optocoupler device HCPL-316 J is provided.Some testing experiments were done.After driving testing,the driving circuit certificates that driving waveforms satisfy the requirements of arc welding power source and the driving circuit is reasonably and simply designed.And the driving circuit has high controlling precision and reliability.No-load-voltage testing and welding external characteristic testing prove that the driving circuit can be applied in arc welding power source.

Nullors, and Nullor Circuits;There Applications in Symbolic Circuit Analysis and Design

The objective in this presentation is to introduce some of the unique properties and applications of nullors in active circuit analysis and designs. The emphasis is to discuss the role nullors can play in symbolic representation of transfer functions. To show this we adopt the topological platform for the circuit analysis and use a recently developed Admittance Method (AM) to achieve the Sum of Tree Products (STP), replacing the determinant and cofactors of the Nodal Admittance Matrix (NAM) of the circuit. To construct a transfer function, we start with a given active circuit and convert all its controlled sources and I/O-ports to nullors. Now, with a solid nullor circuit (passive elements and nullors) we first eliminate the passive elements through AM operations. This produces the STPs. Second, the all-nullor circuit is then used to find the signs or the STPs. Finally, the transfer function (in symbolic, if chosen) is obtained from the ratio between the STPs.

Data-driven fault diagnosis method for analog circuits based on robust competitive agglomeration

The data-driven fault diagnosis methods can improve the reliability of analog circuits by using the data generated from it. The data have some characteristics, such as randomness and incompleteness, which lead to the diagnostic results being sensitive to the specific values and random noise. This paper presents a data-driven fault diagnosis method for analog circuits based on the robust competitive agglomeration （RCA）, which can alleviate the incompleteness of the data by clustering with the competing process. And the robustness of the diagnostic results is enhanced by using the approach of robust statistics in RCA. A series of experiments are provided to demonstrate that RCA can classify the incomplete data with a high accuracy. The experimental results show that RCA is robust for the data needed to be classified as well as the parameters needed to be adjusted. The effectiveness of RCA in practical use is demonstrated by two analog circuits.

Simulation and Design Optimization of Novel Microelectromechanical Digital-to-Analog Converter

A microelectromechanical Digital to Analog Converter (DAC) based on Weighted Gap (WG) principle is described,which is analogous to the weighed resistor DAC in electronic circuits.To convert the input of binary voltage to the output of analog displacement,the gaps are proposed to be employed as a scale factor.A finite element method is used to simulate the performance of the DAC.To reduce the error,the structure design is optimized and the maximum error of 0 002μm is obtained.

Energy-Efficient Large-Scale Antenna Systems with Hybrid Digital-Analog Beamforming Structure

A largescale antenna system （LSAS） with digital beamforming is expected to significantly increase energy efficiency （EE） and spectral efficiency （SE） in a wireless communication system. However, there are many challenging issues related to calibration, energy consumption, and cost in implementing a digital beamforming structure in an LSAS. In a practical LSAS deployment, hybrid digitalanalog beamforming structures with active antennas can be used. In this paper, we investigate the optimal antenna configuration in an N ＆#215; M beamforming structure, where N is the number of transceivers, M is the number of active antennas per transceiver, where analog beamforming is introduced for individual transceivers and digital beamforming is introduced across all N transceivers. We analyze the green point, which is the point of maximum EE on the EESE curve, and show that the logscale EE scales linearly with SE along a slope of lg2/N. We investigate the effect of M on EE for a given SE value in the case of fixed NM and independent N and M. In both cases, there is a unique optimal M that results in optimal EE. In the case of independent N and M, there is no optimal （N, M） combination for optimizing EE. The results of numerical simulations are provided, and these results support our analysis.

Overview of Energy-Efficient Successive-Approximation Analog-to-Digital Converters: State-of-the-Art and a Design Example

This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters （SAR ADCs）. Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert （DAC） and comparator to settle. The 10 bit ADC is simulated in 0.13 μm CMOS process technology. The signal-to-noise and distortion ratio （SNDR） is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330 μW.

Robust Fault Diagnosis of Analog Circuits with Tolerances

A method for robust analog fault diagnosis using hybrid neural networks is proposed. The primary focus of the paper is to provide robust diagnosis using a mechanism to deal with the problem of element tolerances and reduce testing time. The proposed approach is based on the fault dictionary diagnosis method and backward propagation neural network (BPNN) and the adaptive resonance theory (ART) neural network. Simulation results show that the method is robust and fast for fault diagnosis of analog circuits with tolerances.

Optimized Implementation for Wave Digital Filter Based Circuit Emulation on FPGA

A binary tree representation is designed in this paper for optimization of wave digital filter（WDF）implementation.To achieve this,an equivalent WDF model of the original circuit is converted into abinary tree representation at first.This WDF binary tree can then be transformed to several topologies with the same implication,since the WDF adaptors have a symmetrical behavior on their ports.Because the WDF implementation is related to field programmable gate array（FPGA）resource usage and the cycle time of emulation,choosing aproper binary tree topology for WDF implementation can help balance the complexity and performance quality of an emulation system.Both WDF-FPGA emulation and HSpice simulation on the same circuit are tested.There is no significant difference between these two simulations.However,in terms of time consumption,the WDF-FPGA emulation has an advantage over the other.Our experiment also demonstrates that the optimized WDF-FPGA emulation has an acceptable accuracy and feasibility.

THE NEW SUPER-HIGH-SPEED DIGITAL CIRCUIT BASED ON LINEAR AND-OR GATES

The paper reveals the relation between the linear AND-OR gate and the emitter function logic. With theoretic calculation and PSPICE simulation, the paper proves that the linear AND-OR gates can work at super-high-speed and can be multi-cascaded. On the basis of analyzing the high-speed switch units which coordinate with linear AND-OR gates, two kinds of emitter coupled logic circuits are designed. The paper also discusses the design principles of super-high-speed digital circuits, and some examples of combinational and sequential circuits using linear AND-OR gate are given.