新型高分辨率低功耗△-∑模数转换器MCP3422

Mierochip Technology Ine．（美国微芯科技公司）日前宣布推出全新的低功耗、高分辨率△-∑模数转换器（ADC）系列。MCP3422、MCP3423及MCP3424 （MCP3422／3，4）ADC可提供18位分辨率，进行3V连续转换只消耗135mA电流。新款多通道器件均在片上集成了电压参考、可编程增益放大器（PGA）及振荡器，并采用小至2mm×3mm DFN封装，适用于工业、医疗、消费及汽车等市场的便携式测量应用。

Design and Implementation of a Novel Area-Efficient Interpolator

This paper presents the design considerations and implementation of an area-efficient interpolator suitable for a delta-sigma D/A converter. In an effort to reduce the area and design complexity, a method for designing an FIR filter as a tapped cascaded interconnection of identical subfilters is modified. The proposed subfilter structure further minimizes the arithmetic number. Experimental results show that the proposed interpolator achieves the design specification,exhibiting high performance and hardware efficiency,and also has good noise rejection capability. The interpolation filter can be applied to a delta-sigma DAC and is fully functional.

Capacitor self-calibration technique used in time-interleaved successive approximation ADC

A capacitor self-calibration circuit used in a successive approximation analog-to-digital converter （SA-ADC） is presented. This capacitor self-calibration circuit can calibrate erroneous data and work with the ADC by adding an additional clock period. This circuit is used in a 10 bit 32 Msample/s time-interleaved SA- ADC. The chip is implemented with Chart 0. 25 μm 2. 5 V process and totally occupies an area of 1.4 mm× 1.3 mm. After calibration, the simulated signal-to-noise ratio （SNR） is 59. 586 1 dB and the spurious-free dynamic range （SFDR） is 70. 246 dB at 32 MHz. The measured signal-to-noise and distortion ratio （SINAD） is 44. 82 dB and the SFDR is 63. 760 4 dB when the ADC samples a 5.8 MHz sinusoid wave.

Integrated Delta-Sigma 1.5bit Power DAC with 100dB Dynamic Range

A stereo 1.5bit delta-sigma digital-analog converter （△∑ DAC） integrated with a filterless class D power amplifier is introduced. It consumes no static power, and its maximum output power is 436mW with an 8Ω load. Its output dynamic range exceeds 100dB. The circuit is implemented with a TSMC 0. 18μm process. The die area is 0. 28mme. The supply voltage is 1. gV for the digital part and 3.3V for class D.

A Novel Sampling Switch Suitable for Low-Voltage Analog-to-Digital Converters

A novel, highly linear sampling switch suitable for low-voltage operation is proposed. This switch not only eliminates the nonlinearity introduced by gate-source voltage variation, but also reduces the nonlinearity resuiting from threshold voltage variation, which has not been accomplished in earlier low-voltage sampling switches. This is achieved by adopting a replica transistor with the same threshold voltage as the sampling transistor. The effectiveness of this technique is demonstrated by a prototype design of a sampling switch in 0. 35μm. The proposed sampling switch achieves a spurious free dynamic range of 111dB for a 0. 2MHz, 1.2Vp-p input signal, sampled at a rate of 2MS/s,about 18dB over the Bootstrapped switch. Also, the on-resistance variation is reduced by 90%. This method is especially useful for low-voltage, high resolution ADCs, which is a hot topic today.

A Novel Multi-Stage Interpolation Filter Design Technique for High-Resolution Σ-Δ DAC

This paper presents an efficient way to implement an interpolation filter in a 20bit ∑-△ DAC with an oversampling ratio of 128. A multistage structure is used to reduce the complexity of filter coefficients and the fi- nite word length effect. A novel method based on mixed-radix number representation is proposed to realize a poly- phase multiplier-free half-band subfilter with a high resolution. This approach reduces the complexity of the con- trol system and saves chip area dramatically. The IC is realized in a standard 0.13μm CMOS process and the inter- polation filter occupies less than 0.63mm^2 . This realization has desirable properties of regularity with simple hard- ware devices which are suitable for VLSI and can be applied to many other high resolution data converters.

An 80dB Dynamic Range ΣΔ Modulator for Low-IF GSM Receivers

A high-resolution,200kHz signal bandwidth,third-order single-loop single-bit ε△ modulator used in low-IF GSM receivers is presented. The modulator is implemented with fully differential switched capacitor circuits in standard 0. 6μm 2P2M CMOS technology. The modulator uses two balanced reference voltages of ±1V,and is driven by a single 26MHz clock signal. The measurement results show that,with an oversampling ratio of 64, the modulator achieves an 80.6dB dynamic range,a 71.8dB peak SNDR,and a 73.9dB peak SNR in the signal bandwidth of 200kHz. The modulator dissipates 15mW static power from a single 5V supply.

Mismatch Calibration Techniques in Successive Approximation Analog-to-Digital Converters

Comparator offset cancellation and capacitor self-calibration techniques used in a successive approximation analog-to-digital converter （SA-ADC） are described. The calibration circuit works in parallel with the SAADC by adding additional calibration clock cycles to pursue high accuracy and low power consumption, and the calibrated resolution can be up to 14bit. This circuit is used in a 10bit 3Msps successive approximation ADC. This chip is realized with an SMIC 0. 18μm 1.8V process and occupies 0.25mm^2 . It consumes 3. 1mW when operating at 1.8MHz. The measured SINAD is 55. 9068dB, SFDR is 64. 5767dB, and THD is - 74. 8889dB when sampling a 320kHz sine wave.

Spectral Efficiency and Power Allocation for Mixed-ADC Massive MIMO System

This paper investigates the achievable uplink spectral efficiency(SE) of a massive multi-input multi-output(MIMO) system with a mixed analog-to-digital converter(ADC) receiver architecture, in which some antennas are equipped with full-resolution ADCs while others are deployed with low-resolution ADCs. We derive the theoretical results and corresponding approximate expressions of the achievable SE in multi-cell systems with maximum ratio combining(MRC) detector and in single-cell systems with zero-forcing(ZF) detector. Based on approximated results, the effects of physical parameters, including the transmit power, the number of antennas, the proportion of full-resolution ADCs and the quantization precision of the low-resolution ADCs on the achievable SE are revealed. Furthermore, we propose the power allocation algorithms based on the lower bound and upper bound of approximate achievable SE. Our results show that the total achievable SE improves by increasing the number of BS antennas, the signal-to-noise ratio(SNR), and the quantization precision. Results showcase that proposed power allocation algorithms remarkably improve the total achievable SE comparing to the equal power allocation algorithm, which verifies the effectiveness of our proposed schemes.

A 10bit 2GHz CMOS D/A Converter for High-Speed System Applications

This paper presents a 2GS/s 10bit CMOS digital-to-analog converter （DAC） that consists of two unit current-cell matrixes for 6MSBs and 4LSBs, respectively, trading off between the precision and size of the chip. Current mode logic （CML） is used to ensure high speed,and a double centro-symmetric current matrix is designed by the Q^2 random walk strategy in order to ensure the linearity of the DAC. The DAC occupies 2.2mm × 2.2mm of die area and consumes 790mW with a single 3.3V power supply.

Novel Design for High Speed and Resolution Delta-sigma A/D Converter

The delta-sigma converter is one of the high speed and resolution analog-to-digital modulators. Its implementation needs the low oversampling technique and the multi-bit D/A converter. The noise induced by the multi-bit D/A converter becomes one of the key factors deteriorating the signal-to-noise rate of the delta-sigma A/D converter. A novel structure with signal unity transfunction, dynamic element matching(DEM) and noise-shaping is discussed. The method is investigated to design converter based on the proposed structure. The behavior simulation indicates that the structure and the design method are feasible.

Optical-spectrum-encoded analog-to-digital converter

A novel optical-spectrum-encoded （OSE） analog-to-digital converter （ADC） is proposed in this letter. To simply exemplify the conversion idea, a 5-bit device structure consisted of Fabry-Perot interferometers （FPI） is analyzed and numericaly simulated. The dependence of peak-transmission wavelength on modulation voltage in an electro-optical FPI and the dependence of transmitted power on incident light wavelength in an FPI are discussed and utilized to implement OSEADC. A linearly tunable mode-locked laser, as a voltage-wavelength transformer and a sampler, and chirped grating FPIs, as an encoder array, can be used to obtain much greater sampling rate and bit-resolution.

The design of adaptive sigma-delta A/D converter

The signal to noise ratio （SNR） of conventional sigma delta analog to digital converter （∑△ADC） reduces with input signal strength. The existing concept of adaptive quantization is applied to the design of ∑△ADC to improve SNR with high dynamic range. An adaptive algorithm and its circuit implementation is proposed. Because of the error due to the circuit implementation, an error self-calibration circuit is also designed. Simulation results indicate that SNR can he nearly independent of the signal strength.

Asymptotic Analysis for Low-Resolution Massive MIMO Systems with MMSE Receiver

The uplink achievable rate of massive multiple-input-multiple-output(MIMO) systems, where the low-resolution analog-to-digital converters(ADCs) are assumed to equip at the base station(BS), is investigated in this paper. We assume that only imperfect channel station information is known at the BS. Then a new MMSE receiver is designed by taking not only the Gaussian noise, but also the channel estimation error and quantizer noise into account. By using the Stieltjes transform of random matrix, we further derive a tight asymptotic equivalent for the uplink achievable rate with proposed MMSE receiver. We present a detailed analysis for the number of BS antennas through the expression of the achievable rates and validate the results using numerical simulations. It is also shown that we can compensate the performance loss due to the low-resolution quantization by increasing the number of antennas at the BS.

Simulation and Design Optimization of Novel Microelectromechanical Digital-to-Analog Converter

A microelectromechanical Digital to Analog Converter (DAC) based on Weighted Gap (WG) principle is described,which is analogous to the weighed resistor DAC in electronic circuits.To convert the input of binary voltage to the output of analog displacement,the gaps are proposed to be employed as a scale factor.A finite element method is used to simulate the performance of the DAC.To reduce the error,the structure design is optimized and the maximum error of 0 002μm is obtained.

Study of wavelet transform type high-current transformer

The wavelet transformation is applied to the high current transformer.The high current transformer elaborated in the paper is mainly applied to the measurement of AC/DC high current.The principle of the transformer is the Hall direct measurement principle.The transformer has the following three characteristics:firstly, the effect of the remnant field of the iron core on the measurement is decreased;secondly,because the temperature compensation is adopted,the transformer has good temperature charactreristic;thirdly,be cause the wavelet transfomation technology is adopted,the transformer has the capacity of good antijanming.

Optimization and design of inter-stage amplifier with wide output swing,high speed and high accuracy

To satisfy the design requirements of analog-to-digital converter （ADC） of high speed sampling system in an infrared focal plane array tester with 1024 × 1024 pixels, a first inter-stage amplifier of 12-bit 40- Msample/s pipelined ADC was designed with 0. 35 μm CMOS technology. On the basis of traditional two-stage amplifier, the cross-coupled class AB output stage and cascode compensation were adopted to improve the output vohage swing and bandwidth. Power dissipation was optimized with math tools. Circuit and layout design were completed. Simulation results show that the designed amplifier has good performance of 95 dB dc gain, ±2 V output voltage swing, 190 MHz bandwidth and 63° phase margin with feedback factor 1/4, 33 mW power dissipation and so on, which can meet the system requirements.

High Speed Column-Parallel CDS/ADC Circuit with Nonlinearity Compensation for CMOS Image Sensors

A high speed column-parallel CDS/ADC circuit with nonlinearity compensation is proposed in this paper.The correlated double sampling (CDS) and analog-to-digital converter (ADC) functions are integrated in a threephase column-parallel circuit based on two floating gate inverters and switched-capacitor network.The conversion rate of traditional single-slope ADC is speeded up by dividing quantization to coarse step and fine step.A storage capacitor is used to store the result of coarse step and locate the section of ramp signal of fine step,which can reduce the clock step from 2 n to 2 (n/2+1).The floating gate inverters are implemented to reduce the power consumption.Its induced nonlinear offset is cancelled by introducing a compensation module to the input of inverter,which can equalize the coupling path in three phases of the proposed circuit.This circuit is designed and simulated for CMOS image sensor with 640×480 pixel array using Chartered 0.18μm process.Simulation results indicate that the resolution can reach 10-bit and the maximum frame rate can reach 200 frames/s with a main clock of 10MHz.The power consumption of this circuit is less than 36.5μW with a 3.3V power supply.The proposed CDS/ADC circuit is suitable for high resolution and high speed image sensors.