In this paper,we consider the truncated multiplicity finite range set problem of meromorphic functions on some complex disc.By using the value distribution theory of meromorphic functions,we establish a second main th...In this paper,we consider the truncated multiplicity finite range set problem of meromorphic functions on some complex disc.By using the value distribution theory of meromorphic functions,we establish a second main theorem for meromorphic functions with finite growth index which share meromorphic functions(may not be small functions).As its application,we also extend the result of a finite range set with truncated multiplicity.展开更多
The frequency–space（f–x） empirical mode decomposition（EMD） denoising method has two limitations when applied to nonstationary seismic data. First, subtracting the first intrinsic mode function（IMF） results in ...The frequency–space（f–x） empirical mode decomposition（EMD） denoising method has two limitations when applied to nonstationary seismic data. First, subtracting the first intrinsic mode function（IMF） results in signal damage and limited denoising. Second, decomposing the real and imaginary parts of complex data may lead to inconsistent decomposition numbers. Thus, we propose a new method named f–x spatial projection-based complex empirical mode decomposition（CEMD） prediction filtering. The proposed approach directly decomposes complex seismic data into a series of complex IMFs（CIMFs） using the spatial projection-based CEMD algorithm and then applies f–x predictive filtering to the stationary CIMFs to improve the signal-to-noise ratio. Synthetic and real data examples were used to demonstrate the performance of the new method in random noise attenuation and seismic signal preservation.展开更多
The different characteristics of polarization of body and Rayleigh waves make it possible to separate these two types of waves by their characteristics and suppress the latter.The moving time-window analysis often is ...The different characteristics of polarization of body and Rayleigh waves make it possible to separate these two types of waves by their characteristics and suppress the latter.The moving time-window analysis often is used in polarization filtering but it is difficult to determine a suitable time-window length,resulting in some problems,such as complex eigenvalues and non-convergence.For overcoming these disadvantages,in this paper,we introduce the concept of complex-trace analysis and conduct de-noise processing to suppress undesirable surface waves by instantaneous polarization analysis in the case of horizontal and vertical component seismic recordings from the Hauinan coal mine.The performance of the method is illustrated by examples with synthetic and field data and its effectiveness to remove surface waves from multi-component seismic data is demonstrated.展开更多
The design of a 2. 488 Gbit/s clock and data recovery （CDR） If for synchronous digital hierarchy （SDH） STM-16 receiver is described. Based on the injected phase-locked loop （IPLL） and D-flip flop architectures, ...The design of a 2. 488 Gbit/s clock and data recovery （CDR） If for synchronous digital hierarchy （SDH） STM-16 receiver is described. Based on the injected phase-locked loop （IPLL） and D-flip flop architectures, the CDR IC was implemented in a standard 0. 35 μan complementary metal-oxide-semiconductor （CMOS） technology. With 2^31 -1 pseudorandom bit sequences （PRBS） input, the sensitivity of data recovery circuit is less than 20 mV with 10^-12 bit error rate （BER）. The recovered clock shows a root mean square （rms） jitter of 2. 8 ps and a phase noise of - 110 dBc/Hz at 100 kHz offset. The capture range of the circuit is larger than 40 MHz. With a 5 V supply, the circuit consumes 680 mW and the chip area is 1.49 mm × 1 mm.展开更多
A 2.5Gb/s clock and data recovery （CDR） circuit is designed and realized in TSMC＇s standard 0.18/μm CMOS process. The clock recovery is based on a PLL. For phase noise optimization,a dynamic phase and frequency de...A 2.5Gb/s clock and data recovery （CDR） circuit is designed and realized in TSMC＇s standard 0.18/μm CMOS process. The clock recovery is based on a PLL. For phase noise optimization,a dynamic phase and frequency detector （PFD） is used in the PLL. The rms jitter of the recovered 2.5GHz clock is 2.4ps and the SSB phase noise is - 111dBc/Hz at 10kHz offset. The rms jitter of the recovered 2.5Gb/s data is 3.3ps. The power consumption is 120mW.展开更多
A high integrated monolithic IC, with functions of clock recovery, data decision, and 1 ： 4 demultiplexer,is implemented in 0.25μm CMOS process for 2.5Gb/s fiber-optic communications. The recovered and frequency div...A high integrated monolithic IC, with functions of clock recovery, data decision, and 1 ： 4 demultiplexer,is implemented in 0.25μm CMOS process for 2.5Gb/s fiber-optic communications. The recovered and frequency divided 625MHz clock has a phase noise of -106.26dBc/Hz at 100kHz offset in response to a 2.5Gb/s PRBS input data （2^31-1）. The 2.5Gb/s PRBS data are demultiplexed to four 625Mb/s data. The 0.97mm× 0.97mm IC consumes 550mW under a single 3.3V power supply （not including output buffers）.展开更多
Aim The general arbitrary cracked problem in an elastic plane was discussed. Methods For the purpose of acquiring the solution of the problem, a new formulation on the problem was proposed. Compared with the classic...Aim The general arbitrary cracked problem in an elastic plane was discussed. Methods For the purpose of acquiring the solution of the problem, a new formulation on the problem was proposed. Compared with the classical plane elastic crack model, only the known conditions were revised in the new formulation, which are greatly convenient to solve the problem, and no other new condition was given. Results and Conclusion The general exact analytic solution is given here based on the formulation though the problem is very complicated. Furthermore, the stress intensity factors K Ⅰ, K Ⅱ of the problem are also given.展开更多
The basic physics of unsteady Hele-Shaw flow at high Reynolds numbers is mainly studied by an experimental measurement. In order to confirm the Darcy′s law in Hele-Shaw cell, since there is an analogy between flow in...The basic physics of unsteady Hele-Shaw flow at high Reynolds numbers is mainly studied by an experimental measurement. In order to confirm the Darcy′s law in Hele-Shaw cell, since there is an analogy between flow in cells and that in porous media, progressive water waves are utilized to build an unsteady flow in a Hele-Shaw cell, and which complex wave number is measured by a wave height gauge. Meanwhile, theoretical analyses are used to compare with experimental data. Result shows Darcy′s Law is not exactly correct for unsteady Hele-Shaw flows, and it is expected to conduct a modified Darcy′s Law.展开更多
β-SiC ceramic powders were obtained by pyrolyzing polycarbosilane in vacuum at 800-1200 °C. The β-SiC ceramic powders were characterized by TGA/DSC, XRD and Raman spectroscopy. The dielectric properties of β-S...β-SiC ceramic powders were obtained by pyrolyzing polycarbosilane in vacuum at 800-1200 °C. The β-SiC ceramic powders were characterized by TGA/DSC, XRD and Raman spectroscopy. The dielectric properties of β-SiC ceramic powders were investigated by measuring their complex permittivity by rectangle wave guide method in the frequency range of 8.2-18 GHz. The results show that both real part ε′ and imaginary part ε″ of complex permittivity increase with increasing pyrolysis temperature. The mechanism was proposed that order carbon formed at high temperature resulted in electron relaxation polarization and conductance loss, which contributes to the increase in complex permittivity.展开更多
In this paper,a detailed analysis of a phase interpolator for clock recovery is presented. A mathematical model is setup for the phase interpolator and we perform a precise analysis using this model. The result shows ...In this paper,a detailed analysis of a phase interpolator for clock recovery is presented. A mathematical model is setup for the phase interpolator and we perform a precise analysis using this model. The result shows that the output amplitude and linearity of phase interpolator is primarily related to the difference between the two input phases. A new encoding pattern is given to solve this problem. Analysis in the circuit domain was also undertaken. The simulation results show that the relation between RC time-constant and time difference of input clocks affects the linearity of the phase interpolator. To alleviate this undesired effect, two adjustable-RC buffers are added at the input of the PI. Finally,a 90nm CMOS phase interpolator,which can work in the frequency from 1GHz to 5GHz,is proposed. The power dissipation of the phase interpolator is lmW with a 1.2V power supply. Experiment results show that the phase interpolator has a monotone output phase and good linearity.展开更多
The CAD model of molar prosthesis is usually stored in standard templete library （STIr） format. A new topological structure is given based on STL format and the vertex-based entity offset algorithm is presented to r...The CAD model of molar prosthesis is usually stored in standard templete library （STIr） format. A new topological structure is given based on STL format and the vertex-based entity offset algorithm is presented to realize the rapid generation of roughing/finishing tool path for molar prosthesis. Simulation results show that the proposed algorithm prossesses characteristics of excellent stabilization, fast calculation speed and high machining accuracy.展开更多
A 2.5Gb/s/ch data recovery （DR） circuit is designed for an SFI-5 interface. To make the parallel data bit-synchronization and reduce the bit error rate （BER） ,a delay locked loop （DLL） is used to place the cente...A 2.5Gb/s/ch data recovery （DR） circuit is designed for an SFI-5 interface. To make the parallel data bit-synchronization and reduce the bit error rate （BER） ,a delay locked loop （DLL） is used to place the center of the data eye exactly at the rising edge of the data-sampling clock. A single channel DR circuit was fabricated in TSMC＇s standard 0. 18μm CMOS process. The chip area is 0. 46mm^2. With a 2^32 - 1 pseudorandom bit sequence （PRBS） input,the RMS jitter of the recovered 2.5Gb/s data is 3.3ps. The sensitivity of the single channel DR is less than 20mV with 10-12 BER.展开更多
基金Supported by National Natural Science Foundation of China(12061041)Jiangxi Provincial Natural Science Foundation(20232BAB201003).
文摘In this paper,we consider the truncated multiplicity finite range set problem of meromorphic functions on some complex disc.By using the value distribution theory of meromorphic functions,we establish a second main theorem for meromorphic functions with finite growth index which share meromorphic functions(may not be small functions).As its application,we also extend the result of a finite range set with truncated multiplicity.
基金supported financially by the National Natural Science Foundation(No.41174117)the Major National Science and Technology Projects(No.2011ZX05031–001)
文摘The frequency–space（f–x） empirical mode decomposition（EMD） denoising method has two limitations when applied to nonstationary seismic data. First, subtracting the first intrinsic mode function（IMF） results in signal damage and limited denoising. Second, decomposing the real and imaginary parts of complex data may lead to inconsistent decomposition numbers. Thus, we propose a new method named f–x spatial projection-based complex empirical mode decomposition（CEMD） prediction filtering. The proposed approach directly decomposes complex seismic data into a series of complex IMFs（CIMFs） using the spatial projection-based CEMD algorithm and then applies f–x predictive filtering to the stationary CIMFs to improve the signal-to-noise ratio. Synthetic and real data examples were used to demonstrate the performance of the new method in random noise attenuation and seismic signal preservation.
基金supported by the National Natural Science Foundation of China (grant No.40574055)the National 973 Program (Grant No.2006CB202207)the Special Fund (Grant No.2008ZX05035-001-003,2008ZX05035-003-006HZ,2008ZX05008-006-004)
文摘The different characteristics of polarization of body and Rayleigh waves make it possible to separate these two types of waves by their characteristics and suppress the latter.The moving time-window analysis often is used in polarization filtering but it is difficult to determine a suitable time-window length,resulting in some problems,such as complex eigenvalues and non-convergence.For overcoming these disadvantages,in this paper,we introduce the concept of complex-trace analysis and conduct de-noise processing to suppress undesirable surface waves by instantaneous polarization analysis in the case of horizontal and vertical component seismic recordings from the Hauinan coal mine.The performance of the method is illustrated by examples with synthetic and field data and its effectiveness to remove surface waves from multi-component seismic data is demonstrated.
文摘The design of a 2. 488 Gbit/s clock and data recovery （CDR） If for synchronous digital hierarchy （SDH） STM-16 receiver is described. Based on the injected phase-locked loop （IPLL） and D-flip flop architectures, the CDR IC was implemented in a standard 0. 35 μan complementary metal-oxide-semiconductor （CMOS） technology. With 2^31 -1 pseudorandom bit sequences （PRBS） input, the sensitivity of data recovery circuit is less than 20 mV with 10^-12 bit error rate （BER）. The recovered clock shows a root mean square （rms） jitter of 2. 8 ps and a phase noise of - 110 dBc/Hz at 100 kHz offset. The capture range of the circuit is larger than 40 MHz. With a 5 V supply, the circuit consumes 680 mW and the chip area is 1.49 mm × 1 mm.
文摘A 2.5Gb/s clock and data recovery （CDR） circuit is designed and realized in TSMC＇s standard 0.18/μm CMOS process. The clock recovery is based on a PLL. For phase noise optimization,a dynamic phase and frequency detector （PFD） is used in the PLL. The rms jitter of the recovered 2.5GHz clock is 2.4ps and the SSB phase noise is - 111dBc/Hz at 10kHz offset. The rms jitter of the recovered 2.5Gb/s data is 3.3ps. The power consumption is 120mW.
文摘A high integrated monolithic IC, with functions of clock recovery, data decision, and 1 ： 4 demultiplexer,is implemented in 0.25μm CMOS process for 2.5Gb/s fiber-optic communications. The recovered and frequency divided 625MHz clock has a phase noise of -106.26dBc/Hz at 100kHz offset in response to a 2.5Gb/s PRBS input data （2^31-1）. The 2.5Gb/s PRBS data are demultiplexed to four 625Mb/s data. The 0.97mm× 0.97mm IC consumes 550mW under a single 3.3V power supply （not including output buffers）.
文摘Aim The general arbitrary cracked problem in an elastic plane was discussed. Methods For the purpose of acquiring the solution of the problem, a new formulation on the problem was proposed. Compared with the classical plane elastic crack model, only the known conditions were revised in the new formulation, which are greatly convenient to solve the problem, and no other new condition was given. Results and Conclusion The general exact analytic solution is given here based on the formulation though the problem is very complicated. Furthermore, the stress intensity factors K Ⅰ, K Ⅱ of the problem are also given.
文摘The basic physics of unsteady Hele-Shaw flow at high Reynolds numbers is mainly studied by an experimental measurement. In order to confirm the Darcy′s law in Hele-Shaw cell, since there is an analogy between flow in cells and that in porous media, progressive water waves are utilized to build an unsteady flow in a Hele-Shaw cell, and which complex wave number is measured by a wave height gauge. Meanwhile, theoretical analyses are used to compare with experimental data. Result shows Darcy′s Law is not exactly correct for unsteady Hele-Shaw flows, and it is expected to conduct a modified Darcy′s Law.
基金Project (50572090) supported by the National Natural Science Foundation of ChinaProject (KP200901) supported by the Fund of the State Key Laboratory of Solidification Processing, China
文摘β-SiC ceramic powders were obtained by pyrolyzing polycarbosilane in vacuum at 800-1200 °C. The β-SiC ceramic powders were characterized by TGA/DSC, XRD and Raman spectroscopy. The dielectric properties of β-SiC ceramic powders were investigated by measuring their complex permittivity by rectangle wave guide method in the frequency range of 8.2-18 GHz. The results show that both real part ε′ and imaginary part ε″ of complex permittivity increase with increasing pyrolysis temperature. The mechanism was proposed that order carbon formed at high temperature resulted in electron relaxation polarization and conductance loss, which contributes to the increase in complex permittivity.
文摘In this paper,a detailed analysis of a phase interpolator for clock recovery is presented. A mathematical model is setup for the phase interpolator and we perform a precise analysis using this model. The result shows that the output amplitude and linearity of phase interpolator is primarily related to the difference between the two input phases. A new encoding pattern is given to solve this problem. Analysis in the circuit domain was also undertaken. The simulation results show that the relation between RC time-constant and time difference of input clocks affects the linearity of the phase interpolator. To alleviate this undesired effect, two adjustable-RC buffers are added at the input of the PI. Finally,a 90nm CMOS phase interpolator,which can work in the frequency from 1GHz to 5GHz,is proposed. The power dissipation of the phase interpolator is lmW with a 1.2V power supply. Experiment results show that the phase interpolator has a monotone output phase and good linearity.
文摘The CAD model of molar prosthesis is usually stored in standard templete library （STIr） format. A new topological structure is given based on STL format and the vertex-based entity offset algorithm is presented to realize the rapid generation of roughing/finishing tool path for molar prosthesis. Simulation results show that the proposed algorithm prossesses characteristics of excellent stabilization, fast calculation speed and high machining accuracy.
文摘A 2.5Gb/s/ch data recovery （DR） circuit is designed for an SFI-5 interface. To make the parallel data bit-synchronization and reduce the bit error rate （BER） ,a delay locked loop （DLL） is used to place the center of the data eye exactly at the rising edge of the data-sampling clock. A single channel DR circuit was fabricated in TSMC＇s standard 0. 18μm CMOS process. The chip area is 0. 46mm^2. With a 2^32 - 1 pseudorandom bit sequence （PRBS） input,the RMS jitter of the recovered 2.5Gb/s data is 3.3ps. The sensitivity of the single channel DR is less than 20mV with 10-12 BER.
