In this paper,we investigate the strong Feller property of stochastic differential equations(SDEs)with super-linear drift and Hölder diffusion coefficients.By utilizing the Girsanov theorem,coupling method,trunca...In this paper,we investigate the strong Feller property of stochastic differential equations(SDEs)with super-linear drift and Hölder diffusion coefficients.By utilizing the Girsanov theorem,coupling method,truncation method and the Yamada-Watanabe approximation technique,we derived the strong Feller property of the solution.展开更多
The signal integrity problem in 0.18μm CMOS technology is analyzed from simulation.Several rules in this phenomenon are found by analyzing the crosstalk delay and noise,which are helpful for the future circuit design.
Texture and grain boundary character distribution of Cu interconnects with different line width for as-deposited and annealed conditions were measured by EBSD. All specimens appear mixed texture and （111） texture is...Texture and grain boundary character distribution of Cu interconnects with different line width for as-deposited and annealed conditions were measured by EBSD. All specimens appear mixed texture and （111） texture is the dominate component.As-deposited interconnects undergo the phenomenon of self-annealing at RT,in which some abnormally large grains are found. Lower aspect ratio of lines and anneal treatment procured larger grains and stronger （111） texture. Meanwhile, the intensity proportion of other textures with lower strain energy to （111） texture is decreased. As-deposited specimens reveal （111）（112？ and （111） （231） components, （111） （110） component appeared and （111） （112？ and （111） （231） components were developed during the annealing process. High angle boundaries are dominant in all specimens, boundaries with a misorientation of 55°-60° and ∑3 ones in higher proportion, followed by lower boundaries with a misorientation of 35°-40° and 29 boundaries. As the aspect ratio of lines and anneal treatment increase,there is a gradual in- crement in ∑3 boundaries and a decrease in ∑9 boundaries.展开更多
As develops in deep sub micron designs,the interconnect crosstalk becomes much more serious.Espe cially, the coupling inductance can not be ignored in gigahertz designs.So shield insertion is an efficient techniq...As develops in deep sub micron designs,the interconnect crosstalk becomes much more serious.Espe cially, the coupling inductance can not be ignored in gigahertz designs.So shield insertion is an efficient technique to reduce the inductive noise.In this paper,the characteristics of on chip mutual inductance (as well as self) for coplanar,micro stripline and stripline structures are introduced first.Then base on the coplanar interconnect structures,the effective coupling K eff model and the RLC explicit noise model are proposed respectively.The results of experiments show that these two models both have high fidelity.展开更多
Process variations can reduce the accuracy in estimation of interconnect performance. This work presents a process variation based stochastic model and proposes an effective analytical method to estimate interconnect ...Process variations can reduce the accuracy in estimation of interconnect performance. This work presents a process variation based stochastic model and proposes an effective analytical method to estimate interconnect delay. The technique decouples the stochastic interconnect segments by an improved decoupling method. Combined with a polynomial chaos expression （PCE）, this paper applies the stochastic Galerkin method （SGM） to analyze the system response. A finite representation of interconnect delay is then obtained with the complex approximation method and the bisection method. Results from the analysis match well with those from SPICE. Moreover, the method shows good computational efficiency, as the running time is much less than the SPICE simulation＇s.展开更多
A modified reduced-order method for RC networks which takes a division-and-conquest strategy is presented.The whole network is partitioned into a set of sub-networks at first,then each of them is reduced by Krylov sub...A modified reduced-order method for RC networks which takes a division-and-conquest strategy is presented.The whole network is partitioned into a set of sub-networks at first,then each of them is reduced by Krylov subspace techniques,and finally all the reduced sub-networks are incorporated together.With some accuracy,this method can reduce the number of both nodes and components of the circuit comparing to the traditional methods which usually only offer a reduced net with less nodes.This can markedly accelerate the sparse-matrix-based simulators whose performance is dominated by the entity of the matrix or the number of components of the circuits.展开更多
基金Supported by the National Natural Science Foundation of China(11926322)the Fundamental Research Funds for the Central Universities of South-Central MinZu University(CZY22013,3212023sycxjj001)。
文摘In this paper,we investigate the strong Feller property of stochastic differential equations(SDEs)with super-linear drift and Hölder diffusion coefficients.By utilizing the Girsanov theorem,coupling method,truncation method and the Yamada-Watanabe approximation technique,we derived the strong Feller property of the solution.
文摘The signal integrity problem in 0.18μm CMOS technology is analyzed from simulation.Several rules in this phenomenon are found by analyzing the crosstalk delay and noise,which are helpful for the future circuit design.
文摘Texture and grain boundary character distribution of Cu interconnects with different line width for as-deposited and annealed conditions were measured by EBSD. All specimens appear mixed texture and （111） texture is the dominate component.As-deposited interconnects undergo the phenomenon of self-annealing at RT,in which some abnormally large grains are found. Lower aspect ratio of lines and anneal treatment procured larger grains and stronger （111） texture. Meanwhile, the intensity proportion of other textures with lower strain energy to （111） texture is decreased. As-deposited specimens reveal （111）（112？ and （111） （231） components, （111） （110） component appeared and （111） （112？ and （111） （231） components were developed during the annealing process. High angle boundaries are dominant in all specimens, boundaries with a misorientation of 55°-60° and ∑3 ones in higher proportion, followed by lower boundaries with a misorientation of 35°-40° and 29 boundaries. As the aspect ratio of lines and anneal treatment increase,there is a gradual in- crement in ∑3 boundaries and a decrease in ∑9 boundaries.
文摘As develops in deep sub micron designs,the interconnect crosstalk becomes much more serious.Espe cially, the coupling inductance can not be ignored in gigahertz designs.So shield insertion is an efficient technique to reduce the inductive noise.In this paper,the characteristics of on chip mutual inductance (as well as self) for coplanar,micro stripline and stripline structures are introduced first.Then base on the coplanar interconnect structures,the effective coupling K eff model and the RLC explicit noise model are proposed respectively.The results of experiments show that these two models both have high fidelity.
文摘Process variations can reduce the accuracy in estimation of interconnect performance. This work presents a process variation based stochastic model and proposes an effective analytical method to estimate interconnect delay. The technique decouples the stochastic interconnect segments by an improved decoupling method. Combined with a polynomial chaos expression （PCE）, this paper applies the stochastic Galerkin method （SGM） to analyze the system response. A finite representation of interconnect delay is then obtained with the complex approximation method and the bisection method. Results from the analysis match well with those from SPICE. Moreover, the method shows good computational efficiency, as the running time is much less than the SPICE simulation＇s.
文摘A modified reduced-order method for RC networks which takes a division-and-conquest strategy is presented.The whole network is partitioned into a set of sub-networks at first,then each of them is reduced by Krylov subspace techniques,and finally all the reduced sub-networks are incorporated together.With some accuracy,this method can reduce the number of both nodes and components of the circuit comparing to the traditional methods which usually only offer a reduced net with less nodes.This can markedly accelerate the sparse-matrix-based simulators whose performance is dominated by the entity of the matrix or the number of components of the circuits.
