Secondary electron emission(SEE)has emerged as a critical issue in next-generation accelerators.Mitigating SEE on metal surfaces is crucial for enhancing the stability and emittance of particle accelerators while exte...Secondary electron emission(SEE)has emerged as a critical issue in next-generation accelerators.Mitigating SEE on metal surfaces is crucial for enhancing the stability and emittance of particle accelerators while extending their lifespan.This paper explores the application of laser-assisted water jet technology in constructing high-quality micro-trap structures on 316L stainless steel,a key material in accelerator manufacturing.The study systematically analyzes the impact of various parameters such as laser repetition frequency,pulse duration,average power,water jet pressure,repeat times,nozzle offset,focal position,offset distance between grooves,and processing speed on the surface morphology of stainless steel.The findings reveal that micro-groove depth increases with higher laser power but decreases with increasing water jet pressure and processing speed.Interestingly,repeat times have minimal effect on depth.On the other hand,micro-groove width increases with higher laser power and repeat times but decreases with processing speed.By optimizing these parameters,the researchers achieved high-quality pound sign-shaped trap structure with consistent dimensions.We tested the secondary electron emission coefficient of the"well"structure.The coefficient is reduced by 0.5 at most compared to before processing,effectively suppressing secondary electron emission.These results offer indispensable insights for the fabrication of micro-trap structures on material surfaces.Laser-assisted water jet technology demonstrates considerable potential in mitigating SEE on metal surfaces.展开更多
Soil spiders were pitfall-trapped once every month in three forest vegetation types of Ziwuling natural secondary forest region, Gansu Province from April to October, 2004. A total of 2 164 spiders were collected, bel...Soil spiders were pitfall-trapped once every month in three forest vegetation types of Ziwuling natural secondary forest region, Gansu Province from April to October, 2004. A total of 2 164 spiders were collected, belonging to 43 species in 19 families, captured in 630 pitfall trap collections. Linyphiidae, Gnaphosidae and Lycosodae were found to be the dominant families in all habitat types, and the composition of soil spider assemblages was different between the three habitats. Ecological indices of diversity, richness and evenness were significantly different between the three habitats ( P 〈 0.05). The relative abundance of guilds (based on numbers of individuals) varied greatly (P 〈 0.01), which may releet resource availability within habitat types. The existence of different patterns within the assemblages reflects the importance of maintaining habitat heterogeneity and vegetation types in order to preserve soil spider biodiversity.展开更多
A numerical model for bilayer organic light-emitting diodes (OLEDs) is developed under the basis of trapped charge limited conduction.The dependences of the current density on the layer thickness,trap properties and c...A numerical model for bilayer organic light-emitting diodes (OLEDs) is developed under the basis of trapped charge limited conduction.The dependences of the current density on the layer thickness,trap properties and carrier mobility of the hole transport layer (HTL) and emission layer (EML) in bilayer OLEDs of the structure anode/HTL/EML/cathode are numerically investigated.It is found that,for given values of the total thickness of organic layers,reduced depth of trap,total density of trap,and carrier mobility of HTL as well as EML,there exists an optimal thickness ratio of HTL to EML,by which a maximal quantum efficiency can be achieved.Through optimization of the thickness ratio,an enhancement of current density and quantum efficiency of as much as two orders of magnitude can be obtained.The dependences of the optimal thickness ratio to the characteristic trap energy,total density of trap and carrier mobility are numerically analyzed.展开更多
Under heavy nitrogen doping,due to the “concentration quenching” effect,the full spectrum of the NN 3 center is revealed without the interference from the spectra of other higher energy centers.This investigation o...Under heavy nitrogen doping,due to the “concentration quenching” effect,the full spectrum of the NN 3 center is revealed without the interference from the spectra of other higher energy centers.This investigation offers a direct proof for that all the phonon replicas are the phonon sidebands governed by the Huang Rhys’ multiphonon optical transition theory.展开更多
The dependence of the Recombination- Generation( R- G) current on the bulk trap characteristics and sili- con film structure in SOI lateral p+ p- n+ diode has been analyzed num erically by using the simulation tool,D...The dependence of the Recombination- Generation( R- G) current on the bulk trap characteristics and sili- con film structure in SOI lateral p+ p- n+ diode has been analyzed num erically by using the simulation tool,DESSIS- ISE.By varying the bulk trap characteristics such as the trap density and energy level spectrum systematically,the dependence of the R- G current on both of them has been dem onstrated in details.Moreover,the silicon film doping concentration and thickness are changed to make silicon body varies from the fully- depletion m ode into the partial- ly- depletion one.The influence of the transfer of silicon body characteristics on the R- G currenthas also been care- fully examined.A better understanding is obtained of the behavior of bulk trap R- G current in the SOI lateral gat- ed- diode.展开更多
The front gate interface and oxide traps induced by hot carrier stress in SOI NMOSFETs are studied.Based on a new forward gated diode technique,the R G current originating from the front interface traps is me...The front gate interface and oxide traps induced by hot carrier stress in SOI NMOSFETs are studied.Based on a new forward gated diode technique,the R G current originating from the front interface traps is measured,and then the densities of the interface and oxide traps are separated independently.The experimental results show that the hot carrier stress of front channel not only results in the strong generation of the front interface traps,but also in the significant oxide traps.These two kinds of traps have similar characteristic in increasing with the hot carrier stress time.This analysis allows one to obtain a clear physical picture of the effects of the hot carrier stress on the generating of interface and oxide traps,which help to understand the degradation and reliability of the SOI MOSFETs.展开更多
A study of the gate current variation is presented for various thickness ultrathin gate oxides ranging from 1.9 to 3.0nm under the constant voltage stress.The experimental results show the stress induced leakage curre...A study of the gate current variation is presented for various thickness ultrathin gate oxides ranging from 1.9 to 3.0nm under the constant voltage stress.The experimental results show the stress induced leakage current(SILC) includes two parts.One is due to the interface trap-assisted tunneling.The other is owing to the oxide trap-assisted tunneling.展开更多
According to the definition of interface traps,a new application of relaxation spectral technique to sub-threshold swing shift and sub-threshold gate voltage shift is proposed to extract interface trap density in 1.9n...According to the definition of interface traps,a new application of relaxation spectral technique to sub-threshold swing shift and sub-threshold gate voltage shift is proposed to extract interface trap density in 1.9nm MOSFET.And thus the energy distribution of interface trap can be determined.According to the two methods,the energy profile of interface traps agrees with those reported in literature.Compared to other methods,this method is simpler and more convenient.展开更多
The effect of neutral trap on tunneling currentin ultrathin MOSFETs is investigated by num erical analy- sis.The barrier variation arisen by neutral trap in oxide layer is described as a rectangular potential well in...The effect of neutral trap on tunneling currentin ultrathin MOSFETs is investigated by num erical analy- sis.The barrier variation arisen by neutral trap in oxide layer is described as a rectangular potential well in the con- duction band of Si O2 .The different barrier variation of an ultrathin metal- oxide- sem iconductor(MOS) structure with oxide thickness of4nm is numerically calculated.It is shown that the effect of neutral trap on tunneling cur- rent can not be neglected.The tunneling current is increased when the neutral trap exists in the oxide layer.This simple m odel can be used to understand the occurring mechanism of stress induced leakage current.展开更多
A series of slow drain current recovery transients at different gate biases after a short-term stress are observed in an AIGaN/GaN HEMT. As the variation of the time constants of the transients is small, the working t...A series of slow drain current recovery transients at different gate biases after a short-term stress are observed in an AIGaN/GaN HEMT. As the variation of the time constants of the transients is small, the working trap is determined to be electronic. A numerical simulation verifies this conclusion and reproduces the measured transients. The electron traps at different spatial positions in the device-on the ungated surface of the AIGaN layer,in the AIGaN barrier, and in the GaN layer are considered;corresponding behaviors in the stress and the transients are discussed;and for the simulated transients, agreement with and deviation from the measured transients are explained. Based on this discussion, we suggest that the measured transients are caused by the combined effects of a deep surface trap and a bulk trap in the GaN layer.展开更多
By measurement,we investigate the characteristics and location of gate oxide damage induced by snapback stress. The damage incurred during stress causes device degradation that follows an approximate power law with st...By measurement,we investigate the characteristics and location of gate oxide damage induced by snapback stress. The damage incurred during stress causes device degradation that follows an approximate power law with stress time. Oxide traps generated by stress will cause the increase of stress-induced leakage current and the decrease of Qbd (charge to breakdown),and it may also cause the degradation of off-state drain leakage current. Stress-induced gate oxide damage is located not only in the drain side but also in the source side. The tertiary electrons generated by hot holes move toward Si-SiO2 interface under the electrical field toward the substrate,which explains the source side gate oxide damage.展开更多
The generation of oxide charge for 4nm pMOSFETs under hot-carrier stress is investigated by the charge pumping measurements.Firstly,the direct experimental evidences of logarithmic time dependence of hole trapping is ...The generation of oxide charge for 4nm pMOSFETs under hot-carrier stress is investigated by the charge pumping measurements.Firstly,the direct experimental evidences of logarithmic time dependence of hole trapping is observed for pMOSFETs with different channel lengths under hot-carrier stress.Thus,the relationships of oxide charge generation,including electron trapping and hole trapping effects,with different stress voltages and channel lengths are analyzed.It is also found that there is a two-step process in the generation of oxide charge for pMOSFETs.For a short stress time,electron trapping is predominant,whereas for a long stress time,hole trapping dominates the generation of oxide charge.展开更多
A simple new method based on the measurement of charge pumping technique is proposed to separate and quantify experimentally the effects of oxide-trapped charges and interface-trapped charges on threshold voltage degr...A simple new method based on the measurement of charge pumping technique is proposed to separate and quantify experimentally the effects of oxide-trapped charges and interface-trapped charges on threshold voltage degradation in p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) under hot-carrier stress.Further,the experimental results verify the validness of this method.It is shown that,all three mechanisms of electron trapping effect,hole trapping effect and interface trap generation play important roles in p-channel MOSFETs degradation.It is noted that interface-trapped charge is still the dominant mechanism for hot-carrier-induced degradation in p-channel MOSFETs,while a significant contribution of oxide-trapped charge to threshold voltage is demonstrated and quantified.展开更多
Interface traps generated under hot carrier (HC) stress in LDD nMOST's are monitored by the direct current current voltage (DCIV) measurement technique and charge pumping (CP) technique.The measured and analyzed...Interface traps generated under hot carrier (HC) stress in LDD nMOST's are monitored by the direct current current voltage (DCIV) measurement technique and charge pumping (CP) technique.The measured and analyzed results show that the D peak in DCIV spectrum,which related to the drain region,is affected by a superfluous drain leakage current.The band trap band tunneling current is dominant of this current.展开更多
The hot carrier effects under off- state stress m ode( Vgs=0 ,Vds<0 ) have been investigated on9nm P- MOSFETs with channel length varying from1.0 2 5 μm to0 .5 2 5 μm.Both on- and off- state currents are discuss...The hot carrier effects under off- state stress m ode( Vgs=0 ,Vds<0 ) have been investigated on9nm P- MOSFETs with channel length varying from1.0 2 5 μm to0 .5 2 5 μm.Both on- and off- state currents are discussed. It is found that the off- state leakage current decreases after a higher voltage stressing,which is induced by the charge injection occurred close to the drain junction.However,the leakage current increases after a lower voltage stressing because of the newly generated interface traps.It is also found that the on state saturation current and threshold voltage degrade significantly with the stress tim e,which we believe is due to the charges injected near the gate- drain overlapping region and/ or the stress- induced interface trap generation.The degradation of Idsatcan be ex- pressed as a function of the product of the gate current( Ig) and the num ber of charges injected into the gate oxide ( Qinj) in a simple power law.Finally,a lifetime prediction model based on the degradation of Idsatis proposed.展开更多
文摘Secondary electron emission(SEE)has emerged as a critical issue in next-generation accelerators.Mitigating SEE on metal surfaces is crucial for enhancing the stability and emittance of particle accelerators while extending their lifespan.This paper explores the application of laser-assisted water jet technology in constructing high-quality micro-trap structures on 316L stainless steel,a key material in accelerator manufacturing.The study systematically analyzes the impact of various parameters such as laser repetition frequency,pulse duration,average power,water jet pressure,repeat times,nozzle offset,focal position,offset distance between grooves,and processing speed on the surface morphology of stainless steel.The findings reveal that micro-groove depth increases with higher laser power but decreases with increasing water jet pressure and processing speed.Interestingly,repeat times have minimal effect on depth.On the other hand,micro-groove width increases with higher laser power and repeat times but decreases with processing speed.By optimizing these parameters,the researchers achieved high-quality pound sign-shaped trap structure with consistent dimensions.We tested the secondary electron emission coefficient of the"well"structure.The coefficient is reduced by 0.5 at most compared to before processing,effectively suppressing secondary electron emission.These results offer indispensable insights for the fabrication of micro-trap structures on material surfaces.Laser-assisted water jet technology demonstrates considerable potential in mitigating SEE on metal surfaces.
文摘Soil spiders were pitfall-trapped once every month in three forest vegetation types of Ziwuling natural secondary forest region, Gansu Province from April to October, 2004. A total of 2 164 spiders were collected, belonging to 43 species in 19 families, captured in 630 pitfall trap collections. Linyphiidae, Gnaphosidae and Lycosodae were found to be the dominant families in all habitat types, and the composition of soil spider assemblages was different between the three habitats. Ecological indices of diversity, richness and evenness were significantly different between the three habitats ( P 〈 0.05). The relative abundance of guilds (based on numbers of individuals) varied greatly (P 〈 0.01), which may releet resource availability within habitat types. The existence of different patterns within the assemblages reflects the importance of maintaining habitat heterogeneity and vegetation types in order to preserve soil spider biodiversity.
文摘A numerical model for bilayer organic light-emitting diodes (OLEDs) is developed under the basis of trapped charge limited conduction.The dependences of the current density on the layer thickness,trap properties and carrier mobility of the hole transport layer (HTL) and emission layer (EML) in bilayer OLEDs of the structure anode/HTL/EML/cathode are numerically investigated.It is found that,for given values of the total thickness of organic layers,reduced depth of trap,total density of trap,and carrier mobility of HTL as well as EML,there exists an optimal thickness ratio of HTL to EML,by which a maximal quantum efficiency can be achieved.Through optimization of the thickness ratio,an enhancement of current density and quantum efficiency of as much as two orders of magnitude can be obtained.The dependences of the optimal thickness ratio to the characteristic trap energy,total density of trap and carrier mobility are numerically analyzed.
文摘Under heavy nitrogen doping,due to the “concentration quenching” effect,the full spectrum of the NN 3 center is revealed without the interference from the spectra of other higher energy centers.This investigation offers a direct proof for that all the phonon replicas are the phonon sidebands governed by the Huang Rhys’ multiphonon optical transition theory.
基金摩托罗拉和北京大学的联合研究项目!"Gated-Diode Method Application Development and Sensitivity Analysis"的资助 (合同号 :MSPSESTL
文摘The dependence of the Recombination- Generation( R- G) current on the bulk trap characteristics and sili- con film structure in SOI lateral p+ p- n+ diode has been analyzed num erically by using the simulation tool,DESSIS- ISE.By varying the bulk trap characteristics such as the trap density and energy level spectrum systematically,the dependence of the R- G current on both of them has been dem onstrated in details.Moreover,the silicon film doping concentration and thickness are changed to make silicon body varies from the fully- depletion m ode into the partial- ly- depletion one.The influence of the transfer of silicon body characteristics on the R- G currenthas also been care- fully examined.A better understanding is obtained of the behavior of bulk trap R- G current in the SOI lateral gat- ed- diode.
文摘The front gate interface and oxide traps induced by hot carrier stress in SOI NMOSFETs are studied.Based on a new forward gated diode technique,the R G current originating from the front interface traps is measured,and then the densities of the interface and oxide traps are separated independently.The experimental results show that the hot carrier stress of front channel not only results in the strong generation of the front interface traps,but also in the significant oxide traps.These two kinds of traps have similar characteristic in increasing with the hot carrier stress time.This analysis allows one to obtain a clear physical picture of the effects of the hot carrier stress on the generating of interface and oxide traps,which help to understand the degradation and reliability of the SOI MOSFETs.
文摘A study of the gate current variation is presented for various thickness ultrathin gate oxides ranging from 1.9 to 3.0nm under the constant voltage stress.The experimental results show the stress induced leakage current(SILC) includes two parts.One is due to the interface trap-assisted tunneling.The other is owing to the oxide trap-assisted tunneling.
文摘According to the definition of interface traps,a new application of relaxation spectral technique to sub-threshold swing shift and sub-threshold gate voltage shift is proposed to extract interface trap density in 1.9nm MOSFET.And thus the energy distribution of interface trap can be determined.According to the two methods,the energy profile of interface traps agrees with those reported in literature.Compared to other methods,this method is simpler and more convenient.
文摘The effect of neutral trap on tunneling currentin ultrathin MOSFETs is investigated by num erical analy- sis.The barrier variation arisen by neutral trap in oxide layer is described as a rectangular potential well in the con- duction band of Si O2 .The different barrier variation of an ultrathin metal- oxide- sem iconductor(MOS) structure with oxide thickness of4nm is numerically calculated.It is shown that the effect of neutral trap on tunneling cur- rent can not be neglected.The tunneling current is increased when the neutral trap exists in the oxide layer.This simple m odel can be used to understand the occurring mechanism of stress induced leakage current.
文摘A series of slow drain current recovery transients at different gate biases after a short-term stress are observed in an AIGaN/GaN HEMT. As the variation of the time constants of the transients is small, the working trap is determined to be electronic. A numerical simulation verifies this conclusion and reproduces the measured transients. The electron traps at different spatial positions in the device-on the ungated surface of the AIGaN layer,in the AIGaN barrier, and in the GaN layer are considered;corresponding behaviors in the stress and the transients are discussed;and for the simulated transients, agreement with and deviation from the measured transients are explained. Based on this discussion, we suggest that the measured transients are caused by the combined effects of a deep surface trap and a bulk trap in the GaN layer.
文摘By measurement,we investigate the characteristics and location of gate oxide damage induced by snapback stress. The damage incurred during stress causes device degradation that follows an approximate power law with stress time. Oxide traps generated by stress will cause the increase of stress-induced leakage current and the decrease of Qbd (charge to breakdown),and it may also cause the degradation of off-state drain leakage current. Stress-induced gate oxide damage is located not only in the drain side but also in the source side. The tertiary electrons generated by hot holes move toward Si-SiO2 interface under the electrical field toward the substrate,which explains the source side gate oxide damage.
文摘The generation of oxide charge for 4nm pMOSFETs under hot-carrier stress is investigated by the charge pumping measurements.Firstly,the direct experimental evidences of logarithmic time dependence of hole trapping is observed for pMOSFETs with different channel lengths under hot-carrier stress.Thus,the relationships of oxide charge generation,including electron trapping and hole trapping effects,with different stress voltages and channel lengths are analyzed.It is also found that there is a two-step process in the generation of oxide charge for pMOSFETs.For a short stress time,electron trapping is predominant,whereas for a long stress time,hole trapping dominates the generation of oxide charge.
文摘A simple new method based on the measurement of charge pumping technique is proposed to separate and quantify experimentally the effects of oxide-trapped charges and interface-trapped charges on threshold voltage degradation in p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) under hot-carrier stress.Further,the experimental results verify the validness of this method.It is shown that,all three mechanisms of electron trapping effect,hole trapping effect and interface trap generation play important roles in p-channel MOSFETs degradation.It is noted that interface-trapped charge is still the dominant mechanism for hot-carrier-induced degradation in p-channel MOSFETs,while a significant contribution of oxide-trapped charge to threshold voltage is demonstrated and quantified.
文摘Interface traps generated under hot carrier (HC) stress in LDD nMOST's are monitored by the direct current current voltage (DCIV) measurement technique and charge pumping (CP) technique.The measured and analyzed results show that the D peak in DCIV spectrum,which related to the drain region,is affected by a superfluous drain leakage current.The band trap band tunneling current is dominant of this current.
文摘The hot carrier effects under off- state stress m ode( Vgs=0 ,Vds<0 ) have been investigated on9nm P- MOSFETs with channel length varying from1.0 2 5 μm to0 .5 2 5 μm.Both on- and off- state currents are discussed. It is found that the off- state leakage current decreases after a higher voltage stressing,which is induced by the charge injection occurred close to the drain junction.However,the leakage current increases after a lower voltage stressing because of the newly generated interface traps.It is also found that the on state saturation current and threshold voltage degrade significantly with the stress tim e,which we believe is due to the charges injected near the gate- drain overlapping region and/ or the stress- induced interface trap generation.The degradation of Idsatcan be ex- pressed as a function of the product of the gate current( Ig) and the num ber of charges injected into the gate oxide ( Qinj) in a simple power law.Finally,a lifetime prediction model based on the degradation of Idsatis proposed.