A new partitioning methodology is presented to accelerate 130nm and beyond large scale alternating phase shift mask(Alt PSM) design flow.This method deals with granularity self adaptively.Phas...A new partitioning methodology is presented to accelerate 130nm and beyond large scale alternating phase shift mask(Alt PSM) design flow.This method deals with granularity self adaptively.Phase conflicts resolution approaches are described and strategies guaranteeing phase compatible during layout compaction are also discussed.An efficient CAD prototype for dark field Alt PSM based on these algorithms is implemented.The experimental results on several industry layouts show that the tool can successfully cope with the rapid growth of phase conflicts with good quality and satisfy lower resource consumption with different requirements of precision and speedup.展开更多
A novel type of leakage current protector chip,implemented in the mixed-signal 0.6μm CMOS process,is presented. This chip has the advantages of low power dissipation （10mW）, accurate protection control based on dig...A novel type of leakage current protector chip,implemented in the mixed-signal 0.6μm CMOS process,is presented. This chip has the advantages of low power dissipation （10mW）, accurate protection control based on digital response delay time and integration of multi-functions such as leakage current/over-voltage/over-load detection and protection,auto switch-on and so forth. Additionally, the chip is programmable to suit different three-level protection applications with a high anti-interference ability.展开更多
Formal verification is playing a significant role in IC design.However,the common models for verification either have their complexity problems or have applicable limitations.In order to overcome the deficiencies,a no...Formal verification is playing a significant role in IC design.However,the common models for verification either have their complexity problems or have applicable limitations.In order to overcome the deficiencies,a novel model-WGL(Weighted Generalized List)is proposed,which is based on the general-list decomposition of polynomials,with three different weights and manipulation rules introduced to effect node sharing and the canonicity.Timing parameters and operations on them are also considered.Examples show the word-level WGL is the only model to linearly represent the common word-level functions and the bit-level WGL is especially suitable for arithmetic intensive circuits.The model is proved to be a uniform and efficient model for both bit-level and word-level functions.Then based on the WGL model,a backward-construction verification approach is proposed,which reduces time and space complexity for multipliers to polynomial complexity(time complexity is less than O(n3.6)and space complexity is less than O(n1.5))without hierarchical partitioning.Both the model and the verification method show their theoretical and applicable significance in IC design.展开更多
A new power estimation method is proposed for base station(BS) in this paper.Based on this method,a software platform for power estimation is developed.The proposed method models power consumption on different abstrac...A new power estimation method is proposed for base station(BS) in this paper.Based on this method,a software platform for power estimation is developed.The proposed method models power consumption on different abstraction levels by splitting a typical base station into several basic components at different levels in the view of embedded system design.In particular,our focus is on baseband IC(Integrate Circuit) due to it's the dominant power consumer in small cells.Baseband power model is based on arithmetic computing costs of selected algorithms.All computing and storage costs are calibrated using algorithm complexity,hardware architecture,activity ratio,silicon technology,and overheads on all hierarchies.Micro architecture and IC technology are considered.The model enables power comparison of different types of base stations configured with different baseband algorithms,micro architectures,and ICs.The model also supports cellular operators in power estimation of different deployment strategies and transmission schemes.The model is verified by comparing power consumption with a real LTE base station.By exposing more configuration freedoms,the platform can be used for power estimation of current and future base stations.展开更多
To find a design method for 3D active multichannel silicon microelectrode, a microstructure of active neural recording system is presented, where two 2D probes, two integrated circuits and two spacers are microassembl...To find a design method for 3D active multichannel silicon microelectrode, a microstructure of active neural recording system is presented, where two 2D probes, two integrated circuits and two spacers are microassembled on a 5 mm×7 mm silicon platform, and 32 sites neural signals can be operated simultaneously. A theoretical model for measuring the neural signal by the silicon microelectrode is proposed based on the structure and fabrication process of a single-shank probe. The method of determining the dimensional parameters of the probe shank is discussed in the following three aspects, i.e. the structures of pallium and endocranium, coupled interconnecters noise, and strength characteristic of neural probe. The design criterion is to minimize the size of the neural probe as well as that the probe has enough stiffness to pierce the endocranium. The on-chip unity-gain bandpass amplifier has an overall gain of 42 dB over a bandwidth from 60 Hz to 10 kHz; and the DC-baseline stability circuit is of high input resistance above 30 MΩ to guarantee a cutoff frequency below 100 Hz. The circuit works in stimulating or recording modes. The conversion of the modes depends on the stimulating control signal.展开更多
Recently, resonant AC/DC converter has been accepted by the industry. However, the efficiency will be decreased at light load. So, a novel topology with critical controlling mode combined with resonant ones is propose...Recently, resonant AC/DC converter has been accepted by the industry. However, the efficiency will be decreased at light load. So, a novel topology with critical controlling mode combined with resonant ones is proposed in this paper. The new topology can correspond to a 90 plus percent of power converting. So,a novel topology of an state of art integrated circuit, which can be used as power management circuit, has been designed based on the above new topology. A simulator which is specifically suitable for the power controller has been founded in this work and it has been used for the simulation of the novel architecture and the proposed integrated circuit.展开更多
ABC95 array computer is a multi-function network computer based on FPGA technology. A notable feature of ABC95 array computer is the support of complex interconnection, which determines that the computer must have eno...ABC95 array computer is a multi-function network computer based on FPGA technology. A notable feature of ABC95 array computer is the support of complex interconnection, which determines that the computer must have enough I/O band and flexible communications between Pes. The authors designed the interconnecting network chips of ABC95 and realized a form of multi-function interconnection. The multi-function interconnecting network supports conflict-free access from processors to memory matrix and the MESH network of enhanced processors to processor communications. The design scheme has been proved feasible by experiment.展开更多
In the design of the integrated circuits, in order to ensure that the designed products conform to the presupposed parameters, while designing the schematic diagrams of the circuits, we should also strengthen the layo...In the design of the integrated circuits, in order to ensure that the designed products conform to the presupposed parameters, while designing the schematic diagrams of the circuits, we should also strengthen the layout design. Especially in the design of the analog circuits, in the layout design, there is a high degree of matching requirement for the MOS. It will have an important impact on the performance of the chips. Based on this perspective, the author of this paper analyzes how to realize the matching of the three aspects of the MOS, the resistance and the capacitance in the integrated circuit design, in order to avoid the problem of the mismatch due to the arts and crafts.展开更多
The IEEE Standard 1149.1 boundary scan (BS) implementation provides the internal access required for testing the digital printed circuit board (PCB). However, the integrity of the boundary scan test infrastructure sh...The IEEE Standard 1149.1 boundary scan (BS) implementation provides the internal access required for testing the digital printed circuit board (PCB). However, the integrity of the boundary scan test infrastructure should be tested first to guarantee the validation of the results of the rest functional test and diagnosis. This paper describes the fault models and test principles of the BS test access port (TAP) lines on PCBs. A test algorithm with high fault coverage and short time is then presented for the PCB on which all ICs are BS ones.展开更多
文摘A new partitioning methodology is presented to accelerate 130nm and beyond large scale alternating phase shift mask(Alt PSM) design flow.This method deals with granularity self adaptively.Phase conflicts resolution approaches are described and strategies guaranteeing phase compatible during layout compaction are also discussed.An efficient CAD prototype for dark field Alt PSM based on these algorithms is implemented.The experimental results on several industry layouts show that the tool can successfully cope with the rapid growth of phase conflicts with good quality and satisfy lower resource consumption with different requirements of precision and speedup.
文摘A novel type of leakage current protector chip,implemented in the mixed-signal 0.6μm CMOS process,is presented. This chip has the advantages of low power dissipation （10mW）, accurate protection control based on digital response delay time and integration of multi-functions such as leakage current/over-voltage/over-load detection and protection,auto switch-on and so forth. Additionally, the chip is programmable to suit different three-level protection applications with a high anti-interference ability.
基金Sponsored by the National Natural Science Foundation of China(Grant No.69973014and60273081)the Natural Science Foundation of Heilongjiang Province(Grant No.F0209)HEU Foundation(Grant No.HEUF04088).
文摘Formal verification is playing a significant role in IC design.However,the common models for verification either have their complexity problems or have applicable limitations.In order to overcome the deficiencies,a novel model-WGL(Weighted Generalized List)is proposed,which is based on the general-list decomposition of polynomials,with three different weights and manipulation rules introduced to effect node sharing and the canonicity.Timing parameters and operations on them are also considered.Examples show the word-level WGL is the only model to linearly represent the common word-level functions and the bit-level WGL is especially suitable for arithmetic intensive circuits.The model is proved to be a uniform and efficient model for both bit-level and word-level functions.Then based on the WGL model,a backward-construction verification approach is proposed,which reduces time and space complexity for multipliers to polynomial complexity(time complexity is less than O(n3.6)and space complexity is less than O(n1.5))without hierarchical partitioning.Both the model and the verification method show their theoretical and applicable significance in IC design.
基金The finance supporting from National High Technical Research and Development Program of China(863program)2014AA01A705
文摘A new power estimation method is proposed for base station(BS) in this paper.Based on this method,a software platform for power estimation is developed.The proposed method models power consumption on different abstraction levels by splitting a typical base station into several basic components at different levels in the view of embedded system design.In particular,our focus is on baseband IC(Integrate Circuit) due to it's the dominant power consumer in small cells.Baseband power model is based on arithmetic computing costs of selected algorithms.All computing and storage costs are calibrated using algorithm complexity,hardware architecture,activity ratio,silicon technology,and overheads on all hierarchies.Micro architecture and IC technology are considered.The model enables power comparison of different types of base stations configured with different baseband algorithms,micro architectures,and ICs.The model also supports cellular operators in power estimation of different deployment strategies and transmission schemes.The model is verified by comparing power consumption with a real LTE base station.By exposing more configuration freedoms,the platform can be used for power estimation of current and future base stations.
基金Supported by Tianjin Municipal Science and Technology Commission(No. 05YFSYSF01700).
文摘To find a design method for 3D active multichannel silicon microelectrode, a microstructure of active neural recording system is presented, where two 2D probes, two integrated circuits and two spacers are microassembled on a 5 mm×7 mm silicon platform, and 32 sites neural signals can be operated simultaneously. A theoretical model for measuring the neural signal by the silicon microelectrode is proposed based on the structure and fabrication process of a single-shank probe. The method of determining the dimensional parameters of the probe shank is discussed in the following three aspects, i.e. the structures of pallium and endocranium, coupled interconnecters noise, and strength characteristic of neural probe. The design criterion is to minimize the size of the neural probe as well as that the probe has enough stiffness to pierce the endocranium. The on-chip unity-gain bandpass amplifier has an overall gain of 42 dB over a bandwidth from 60 Hz to 10 kHz; and the DC-baseline stability circuit is of high input resistance above 30 MΩ to guarantee a cutoff frequency below 100 Hz. The circuit works in stimulating or recording modes. The conversion of the modes depends on the stimulating control signal.
基金supported by Program for New Century Excellent Talents in University(NCET)(2008)Funding Project for Academic Human Resources Development in Institutions of Higher Learning Under the Jurisdiction of Beijing Municipality+1 种基金 (PHR(IHLB)) and Beijing Novel Research Star(2005B01)Ministry of Beijing Science and Technology
文摘Recently, resonant AC/DC converter has been accepted by the industry. However, the efficiency will be decreased at light load. So, a novel topology with critical controlling mode combined with resonant ones is proposed in this paper. The new topology can correspond to a 90 plus percent of power converting. So,a novel topology of an state of art integrated circuit, which can be used as power management circuit, has been designed based on the above new topology. A simulator which is specifically suitable for the power controller has been founded in this work and it has been used for the simulation of the novel architecture and the proposed integrated circuit.
文摘ABC95 array computer is a multi-function network computer based on FPGA technology. A notable feature of ABC95 array computer is the support of complex interconnection, which determines that the computer must have enough I/O band and flexible communications between Pes. The authors designed the interconnecting network chips of ABC95 and realized a form of multi-function interconnection. The multi-function interconnecting network supports conflict-free access from processors to memory matrix and the MESH network of enhanced processors to processor communications. The design scheme has been proved feasible by experiment.
文摘In the design of the integrated circuits, in order to ensure that the designed products conform to the presupposed parameters, while designing the schematic diagrams of the circuits, we should also strengthen the layout design. Especially in the design of the analog circuits, in the layout design, there is a high degree of matching requirement for the MOS. It will have an important impact on the performance of the chips. Based on this perspective, the author of this paper analyzes how to realize the matching of the three aspects of the MOS, the resistance and the capacitance in the integrated circuit design, in order to avoid the problem of the mismatch due to the arts and crafts.
文摘The IEEE Standard 1149.1 boundary scan (BS) implementation provides the internal access required for testing the digital printed circuit board (PCB). However, the integrity of the boundary scan test infrastructure should be tested first to guarantee the validation of the results of the rest functional test and diagnosis. This paper describes the fault models and test principles of the BS test access port (TAP) lines on PCBs. A test algorithm with high fault coverage and short time is then presented for the PCB on which all ICs are BS ones.
